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1. 发明申请

US20140047151A1 INTERRUPT PROCESSING UNIT FOR PREVENTING INTERRUPT LOSS 有权
标题翻译：用于防止中断丢失的中断处理单元
公开(公告)号：US20140047151A1
公开(公告)日：2014-02-13
申请号：US13571051
申请日：2012-08-09
申请人： John R. Feehrer , Fred Han-Ching Tsai , Ali Vahidsafa , Sumti Jairath
发明人： John R. Feehrer , Fred Han-Ching Tsai , Ali Vahidsafa , Sumti Jairath
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F1/24 , G06F1/3203 , G06F9/4812
摘要： Techniques are disclosed relating to systems that allow sending and receiving of interrupts between processing elements. In various embodiments, a system includes an interrupt processing unit that in turn includes various indicators corresponding to processing elements. In some embodiments, the interrupt processing unit may be configured to receive an interrupt and determine whether a first processing element associated with the interrupt is available to receive interrupts. The system may initiate a corrective action if the first processing element is not available to receive interrupts. In some embodiments, the corrective action may include redirecting the interrupt to a second processing element. In some embodiments, the interrupt processing unit may include a dropped interrupt management register to store information corresponding to the second processing element. In some embodiments, the corrective action may include altering the power state of the first processing element such that it becomes available to receive interrupts.
摘要翻译：公开了涉及允许发送和接收处理元件之间的中断的系统的技术。在各种实施例中，系统包括中断处理单元，该中断处理单元又包括对应于处理元件的各种指示符。在一些实施例中，中断处理单元可以被配置为接收中断并且确定与该中断相关联的第一处理单元是否可用于接收中断。如果第一处理元件不可用于接收中断，则系统可以发起校正动作。在一些实施例中，校正动作可以包括将中断重定向到第二处理元件。在一些实施例中，中断处理单元可以包括丢弃的中断管理寄存器来存储对应于第二处理单元的信息。在一些实施例中，校正动作可以包括改变第一处理元件的功率状态，使得其可用于接收中断。

2. 发明申请

US20130311814A1 CONSTANT FREQUENCY ARCHITECTURAL TIMER IN A DYNAMIC CLOCK DOMAIN 有权
标题翻译：动态时钟域中的恒定频率建筑定时器
公开(公告)号：US20130311814A1
公开(公告)日：2013-11-21
申请号：US13472105
申请日：2012-05-15
申请人： Sebastian Turullols , Ali Vahidsafa
发明人： Sebastian Turullols , Ali Vahidsafa
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： G06F1/14 , G06F1/12 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system.
摘要翻译：本公开的实现涉及一种用于为经变化的核心时钟信号操作的微处理器提供恒定频率定时器信号的装置和/或方法。该装置和/或方法利用码本发生器，例如灰度代码发生器，其操作在允许恒定频率定时器信号比核心时钟频率更快或更慢的参考时钟信号。更具体地，装置和/或方法可以计算先前灰度代码样本之间的差异，并将计算出的差值加到软件可见参考时钟信号上，使得恒定频率定时器信号可以比核心时钟信号更快或更慢。通过使用装置和/或方法，可以根据需要减少核心时钟信号，以在维持计算系统的执行程序之间的同步的同时，使微处理器和采用本文描述的技术的计算系统提供操作功率节省。

3. 发明申请

US20110072326A1 SRAM MACRO TEST FLOP 有权
标题翻译： SRAM宏测试平台
公开(公告)号：US20110072326A1
公开(公告)日：2011-03-24
申请号：US12565689
申请日：2009-09-23
申请人： Ali Vahidsafa , Robert P. Masleid , Jason M. Hart , Zhirong Feng
发明人： Ali Vahidsafa , Robert P. Masleid , Jason M. Hart , Zhirong Feng
IPC分类号： G06F11/00 , G06F12/00
CPC分类号： G01R31/318541 , G11C11/41 , G11C29/003 , G11C29/22 , G11C29/32 , G11C29/48
摘要： A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.
摘要翻译： SRAM（静态随机存取存储器）宏测试电路包括触发电路，扫描控制电路和输出缓冲电路。触发器电路包括主锁存电路和从锁存电路。主锁存电路包括主反馈电路，主电路包括主存储节点和主前馈电路。从锁存电路包括从主存储节点和从主锁存器驱动的从前馈电路的从属反馈电路。扫描控制电路包括扫描从机前馈电路，扫描锁存电路和由扫描反馈电路驱动的扫描驱动电路。扫描锁存电路包括扫描反馈电路，其包括从从锁存器驱动的扫描存储节点和扫描前馈电路。输出缓冲电路包括从主锁存电路驱动的主驱动器和从从锁存电路驱动的从驱动器。

4. 发明授权

US4920485A Method and apparatus for arbitration and serialization in a multiprocessor system 失效
标题翻译：多处理器系统中仲裁和序列化的方法和装置
公开(公告)号：US4920485A
公开(公告)日：1990-04-24
申请号：US239067
申请日：1988-08-31
申请人： Ali Vahidsafa
发明人： Ali Vahidsafa
IPC分类号： G06F9/38 , G06F13/14 , G06F15/17
CPC分类号： G06F9/3879 , G06F13/14 , G06F15/17
摘要： A method and apparatus for providing arbitration between and serialization of plural processors in a multiprocessor system comprising, in each processor, a delay network, a priority circuit, a REQUEST generator, an ORDER generator, a serialization program, an ACK generator and an ACK receiver. In operation, the delay network insures that simultaneously generated REQUESTS received from plural processors are received by the priority circuit at the same time. A processor awarded priority issues an ORDER to the other processors and thereafter drops its REQUEST to allow an award of priority to another processor. An ACK is received by the ORDER issuing processor from each processor when it executes the ORDER. The ORDER issuing processor then completes the task which gave rise to the ORDER. To conserve processing time, priority awards may be made before previously issued ORDERS are completed. Alternatively, REQUEST issuing processors can simply hold their REQUEST and thereby prevent interruption of instructions or groups of instructions.
摘要翻译：一种用于在多处理器系统中提供多个处理器之间的仲裁和串行化的方法和装置，包括在每个处理器中，延迟网络，优先级电路，REQUEST生成器，ORDER发生器，串行化程序，ACK发生器和ACK接收器。在操作中，延迟网络确保同时生成的从多个处理器接收的请求被优先级电路同时接收。一个处理器向其他处理器授予优先级问题，然后丢弃其REQUEST以允许将优先级授予另一个处理器。当执行ORDER时，ORDER发行处理器从每个处理器接收到ACK。然后ORDER发布处理器完成导致ORDER的任务。为节省处理时间，优先奖励可能在之前发布的订单完成之前进行。或者，REQUEST发出处理器可以简单地保持其请求，从而防止指令或指令组的中断。

5. 发明授权

US09026705B2 Interrupt processing unit for preventing interrupt loss 有权
标题翻译：用于防止中断丢失的中断处理单元
公开(公告)号：US09026705B2
公开(公告)日：2015-05-05
申请号：US13571051
申请日：2012-08-09
申请人： John R. Feehrer , Fred Han-Ching Tsai , Ali Vahidsafa , Sumti Jairath
发明人： John R. Feehrer , Fred Han-Ching Tsai , Ali Vahidsafa , Sumti Jairath
IPC分类号： G06F13/24 , G06F9/48
CPC分类号： G06F13/24 , G06F1/24 , G06F1/3203 , G06F9/4812
摘要： Techniques are disclosed relating to systems that allow sending and receiving of interrupts between processing elements. In various embodiments, a system includes an interrupt processing unit that in turn includes various indicators corresponding to processing elements. In some embodiments, the interrupt processing unit may be configured to receive an interrupt and determine whether a first processing element associated with the interrupt is available to receive interrupts. The system may initiate a corrective action if the first processing element is not available to receive interrupts. In some embodiments, the corrective action may include redirecting the interrupt to a second processing element. In some embodiments, the interrupt processing unit may include a dropped interrupt management register to store information corresponding to the second processing element. In some embodiments, the corrective action may include altering the power state of the first processing element such that it becomes available to receive interrupts.
摘要翻译：公开了涉及允许发送和接收处理元件之间的中断的系统的技术。在各种实施例中，系统包括中断处理单元，该中断处理单元又包括对应于处理元件的各种指示符。在一些实施例中，中断处理单元可以被配置为接收中断并且确定与该中断相关联的第一处理单元是否可用于接收中断。如果第一处理元件不可用于接收中断，则系统可以发起校正动作。在一些实施例中，校正动作可以包括将中断重定向到第二处理元件。在一些实施例中，中断处理单元可以包括丢弃的中断管理寄存器来存储对应于第二处理单元的信息。在一些实施例中，校正动作可以包括改变第一处理元件的功率状态，使得其可用于接收中断。

6. 发明授权

US09015460B2 Hybrid hardwired/programmable reset sequence controller 有权
标题翻译：混合硬连线/可编程复位序列控制器
公开(公告)号：US09015460B2
公开(公告)日：2015-04-21
申请号：US13561859
申请日：2012-07-30
申请人： Ali Vahidsafa
发明人： Ali Vahidsafa
IPC分类号： G06F1/24 , G06F11/27
CPC分类号： G06F1/24 , G06F11/27
摘要： A processor having a number of functional units includes a hybrid reset sequence controller that includes a master reset controller that may be configured to hierarchically control a sequence of initialization operations performed on the functional units based upon a value stored within a master control register. In addition, the processor may also include a number of additional controllers, each configured to control initialization operations for a respective functional unit based upon a value stored within an additional respective control register. The master reset controller may control each of the additional reset controllers dependent on the value stored within the master control register.
摘要翻译：具有多个功能单元的处理器包括混合重置序列控制器，其包括主复位控制器，其可以被配置为基于存储在主控制寄存器内的值对功能单元执行的初始化操作的顺序进行分层控制。此外，处理器还可以包括多个附加控制器，每个附加控制器被配置为基于存储在附加的相应控制寄存器内的值来控制各个功能单元的初始化操作。主复位控制器可以根据存储在主控制寄存器中的值来控制每个附加复位控制器。

7. 发明申请

US20140082396A1 METHOD AND APPARATUS FOR DISTRIBUTED GENERATION OF MULTIPLE CONFIGURABLE RATIOED CLOCK DOMAINS WITHIN A HIGH SPEED DOMAIN 有权
标题翻译：用于在高速域中分布式生成多个可配置比例时钟域的方法和装置
公开(公告)号：US20140082396A1
公开(公告)日：2014-03-20
申请号：US13619733
申请日：2012-09-14
申请人： Ali Vahidsafa , Robert Paul Masleid
发明人： Ali Vahidsafa , Robert Paul Masleid
IPC分类号： G06F1/12 , G06F1/06
CPC分类号： G06F1/12 , G06F1/06 , G06F1/10
摘要： Implementations of the present disclosure involve an apparatus and/or method for providing one or more clock signals within a processing device. In particular, one or more counter devices may be integrated into a microprocessor design that operates on a system clock signal to provide ratioed synchronous clock signals for use by the microprocessor. Additionally, one or more synchronization pulse signals are also generated from the one or more counter devices to facilitate communication between domains of the microprocessor that may operate on separate clock frequencies. Such synchronization pulse signals may also provide for a virtual clock signal within a clock domain to create a low frequency logic cluster within a high frequency domain of the microprocessor. A synchronous, low frequency reset signal is also disclosed to synchronize the counting devices to the system clock without the need for an additional high frequency signal path in the microprocessor design.
摘要翻译：本公开的实现涉及用于在处理设备内提供一个或多个时钟信号的装置和/或方法。特别地，一个或多个计数器装置可以集成到微处理器设计中，该微处理器设计基于系统时钟信号进行操作，以提供比率的同步时钟信号供微处理器使用。此外，还从一个或多个计数器装置产生一个或多个同步脉冲信号，以促进可在单独的时钟频率上操作的微处理器的区域之间的通信。这种同步脉冲信号还可以提供时钟域内的虚拟时钟信号，以在微处理器的高频域内创建低频逻辑簇。还公开了同步低频复位信号，以使计数器件与系统时钟同步，而不需要微处理器设计中的额外的高频信号路径。

8. 发明授权

US08990606B2 Constant frequency architectural timer in a dynamic clock domain 有权
标题翻译：动态时钟域中的恒定频率架构定时器
公开(公告)号：US08990606B2
公开(公告)日：2015-03-24
申请号：US13472105
申请日：2012-05-15
申请人： Sebastian Turullols , Ali Vahidsafa
发明人： Sebastian Turullols , Ali Vahidsafa
IPC分类号： G06F1/00 , H03K5/01 , H03L7/00 , G06F1/12 , G06F1/14
CPC分类号： G06F1/14 , G06F1/12 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system.
摘要翻译：本公开的实现涉及一种用于为经变化的核心时钟信号操作的微处理器提供恒定频率定时器信号的装置和/或方法。该装置和/或方法利用码本发生器，例如灰度代码发生器，其操作在允许恒定频率定时器信号比核心时钟频率更快或更慢的参考时钟信号。更具体地，装置和/或方法可以计算先前灰度代码样本之间的差异，并将计算出的差值加到软件可见参考时钟信号上，使得恒定频率定时器信号可以比核心时钟信号更快或更慢。通过使用装置和/或方法，可以根据需要减少核心时钟信号，以在维持计算系统的执行程序之间的同步的同时，使微处理器和采用本文描述的技术的计算系统提供操作功率节省。

9. 发明授权

US08943375B2 Combo static flop with full test 有权
标题翻译：组合静态触发器充分测试
公开(公告)号：US08943375B2
公开(公告)日：2015-01-27
申请号：US13569833
申请日：2012-08-08
申请人： Robert P. Masleid , Ali Vahidsafa
发明人： Robert P. Masleid , Ali Vahidsafa
IPC分类号： G11C29/32 , G11C29/54
CPC分类号： G11C29/32
摘要： A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master storage node and a multiplexer. The slave latch circuit includes a slave storage node driven by the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from the master latch circuit and a slave driver driven from the slave latch circuit.
摘要翻译： SRAM（静态随机存取存储器）宏测试电路包括触发电路，扫描控制电路和输出缓冲电路。触发器电路包括主锁存电路和从锁存电路。主锁存电路包括主存储节点和多路复用器。从锁存电路包括由主锁存器驱动的从存储节点。扫描控制电路包括扫描从机前馈电路，扫描锁存电路和由扫描反馈电路驱动的扫描驱动电路。扫描锁存电路包括扫描反馈电路，扫描存储节点和从从锁存器驱动的扫描前馈电路。输出缓冲电路包括从主锁存电路驱动的主驱动器和从从锁存电路驱动的从驱动器。

10. 发明申请

US20140062548A1 WIDE-RANGE GLITCH-FREE ASYNCHRONOUS CLOCK SWITCH 有权
标题翻译：宽屏无刷异步时钟开关
公开(公告)号：US20140062548A1
公开(公告)日：2014-03-06
申请号：US13604795
申请日：2012-09-06
申请人： Changku Hwang , Sebastian Turullols , Daisy Jian , Ali Vahidsafa
发明人： Changku Hwang , Sebastian Turullols , Daisy Jian , Ali Vahidsafa
IPC分类号： H03L7/00 , H03L7/06
CPC分类号： H03K5/135
摘要： Embodiments include systems and methods for asynchronous, glitch-free clock switching across a wide range of clock frequencies with minimal clock down time. Embodiments effectively provide two stages of synchronization across two independent clock domains. In a first synchronization stage, a received, asynchronous clock select signal is translated into a synchronized clock select signal that is effectively synchronous with respect to a first clock domain and is still effectively asynchronous with respect to a second clock domain. In a second synchronization stage, the synchronized clock select signal is resynchronized so as to be effectively synchronous with respect to the second clock domain. The synchronized select signal can be used to disable the clock of the first clock domain, and the resynchronized clock select signal can be used to enable the clock of the second clock domain.
摘要翻译：实施例包括用于在具有最小时钟停机时间的宽范围的时钟频率上进行异步，无毛刺时钟切换的系统和方法。实施例有效地提供跨两个独立时钟域的两个阶段的同步。在第一同步阶段，接收到的异步时钟选择信号被转换成相对于第一时钟域有效同步的同步时钟选择信号，并且相对于第二时钟域仍然有效地是异步的。在第二同步级中，同步的时钟选择信号被重新同步，以便相对于第二时钟域有效地同步。同步选择信号可用于禁用第一时钟域的时钟，并且重新同步的时钟选择信号可用于启用第二时钟域的时钟。

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