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1. 发明授权

US11456596B2 USB type-C load switch ESD protection 有权
公开(公告)号：US11456596B2
公开(公告)日：2022-09-27
申请号：US17205866
申请日：2021-03-18
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Shekar Mallikarjunaswamy
IPC分类号： H02H9/04 , H01L23/60 , H01L23/495 , H01L27/02 , H01L25/18 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/49 , H01L29/735 , H01L29/78 , H01L29/861
摘要： A MOSFET and an electrostatic discharge (ESD) protection device on a common chip includes a MOSFET with a source, a gate, and a drain, and an ESD protection device configured to implement a diode function that is biased to prevent current from flowing through the common chip from the source to the drain.

2. 发明授权

US10109625B2 JFET and LDMOS transistor formed using deep diffusion regions 有权
公开(公告)号：US10109625B2
公开(公告)日：2018-10-23
申请号：US15804598
申请日：2017-11-06
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Shekar Mallikarjunaswamy
IPC分类号： H01L27/085 , H01L21/8234 , H01L21/265 , H01L21/8232 , H01L29/06 , H01L29/10 , H01L29/78 , H01L29/36 , H01L29/66 , H01L29/808
摘要： A power integrated circuit and a method of forming includes forming a first body region of a first conductivity type in a first deep well of a second conductivity type. The power integrated circuit includes a first deep diffusion region formed under the first body region and in electrical contact with the first body region where the first deep diffusion region is formed by performing first and second ion implantations of dopants of the first conductivity type and using second implant energy greater than the first implant energy.

3. 发明授权

US09837386B2 Power device and preparation method thereof 有权
公开(公告)号：US09837386B2
公开(公告)日：2017-12-05
申请号：US14993971
申请日：2016-01-12
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Xiaotian Zhang , Shekar Mallikarjunaswamy , Zhiqiang Niu , Cheow Khoon Oh , Yueh-Se Ho
IPC分类号： H01L25/07 , H01L23/49 , H02M3/158 , H01L29/78 , H01L23/498 , H01L23/00
CPC分类号： H01L25/072 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L24/17 , H01L24/37 , H01L24/40 , H01L24/73 , H01L25/16 , H01L29/7827 , H01L2224/16225 , H01L2224/376 , H01L2224/4005 , H01L2224/40137 , H01L2224/73255 , H01L2224/84801 , H01L2924/00014 , H01L2924/13091 , H01L2924/14252 , H02M3/158 , H01L2224/37599
摘要： A power conversion device including a low-side MOSFET, a high-side MOSFET and an integrated control IC chip is disclosed. The power conversion device further includes a substrate comprising a first mounting area having a first group of welding discs and a second mounting area having a second group of welding discs; a first chip flipped and attached to the first mounting area; a second chip flipped and attached to the second mounting area; a metal clip; and a molding body covering a front surface of the substrate, the first chip, the second chip and the metal clip. Metal pads on a front side of the first chip is attached to the first group of welding discs. Metal pads on a front side of the second chip is attached to the second group of welding discs. The metal clip connects a connection pad to a back metal layer of the first chip.

4. 发明授权

US09460926B2 Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions 有权
标题翻译：在使用深扩散区域的单片功率集成电路中形成JFET和LDMOS晶体管
公开(公告)号：US09460926B2
公开(公告)日：2016-10-04
申请号：US14320434
申请日：2014-06-30
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Shekar Mallikarjunaswamy
IPC分类号： H01L27/06 , H01L21/265 , H01L29/78 , H01L29/808 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/36 , H01L21/8232 , H01L27/085
CPC分类号： H01L27/085 , H01L21/26513 , H01L21/8232 , H01L21/8234 , H01L29/063 , H01L29/0878 , H01L29/1066 , H01L29/1095 , H01L29/36 , H01L29/42368 , H01L29/66681 , H01L29/66901 , H01L29/7816 , H01L29/7817 , H01L29/7823 , H01L29/808
摘要： A power integrated circuit includes a junction field effect transistor (JFET) device formed in a first portion of a semiconductor layer with a gate region being formed using a first body region, and a double-diffused metal-oxide-semiconductor (LDMOS) transistor formed in a second portion of the semiconductor layer with a channel being formed in a second body region. The power integrated circuit includes a first deep diffusion region formed under the first body region and in electrical contact with the first body region where the first deep diffusion region together with the firs body region establish a pinch off voltage of the JFET device; and a second deep diffusion region formed under the second body region and in electrical contact with the second body region where the second deep diffusion region forms a reduced surface field (RESURF) structure in the LDMOS transistor.
摘要翻译：功率集成电路包括在半导体层的第一部分中形成的结场效应晶体管（JFET）器件，其栅极区域使用第一体区形成，并且形成双扩散金属氧化物半导体（LDMOS）晶体管在半导体层的第二部分中，沟道形成在第二体区中。功率集成电路包括形成在第一体区下并与第一体区电接触的第一深扩散区，其中第一深扩散区与第一体区一起建立JFET器件的夹断电压; 以及形成在所述第二体区下并与所述第二体区的电接触的第二深扩散区，其中所述第二深扩散区在所述LDMOS晶体管中形成减小的表面场（RESURF）结构。

5. 发明申请

US20160247895A1 LATERAL PNP BIPOLAR TRANSISTOR WITH NARROW TRENCH EMITTER 审中-公开
标题翻译：带NARROW TRENCH发射器的侧向PNP双极晶体管
公开(公告)号：US20160247895A1
公开(公告)日：2016-08-25
申请号：US15057461
申请日：2016-03-01
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Shekar Mallikarjunaswamy , Francois Hebert
IPC分类号： H01L29/66 , H01L21/02 , H01L21/762 , H01L21/225 , H01L29/08 , H01L29/06 , H01L21/311 , H01L21/324
CPC分类号： H01L29/6625 , H01L21/02532 , H01L21/02595 , H01L21/2254 , H01L21/31111 , H01L21/324 , H01L21/76224 , H01L29/0649 , H01L29/0808 , H01L29/735
摘要： A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.
摘要翻译：横向双极晶体管包括沟槽发射极和沟槽集电极区域，以形成超窄的发射极区域，从而提高发射极效率。使用相同的沟槽工艺来形成发射极/集电极沟槽以及沟槽隔离结构，使得不需要额外的处理步骤来形成沟槽发射极和集电极。在本发明的实施例中，可以使用离子注入形成在半导体层中的沟槽中形成沟槽发射极和沟槽集电极区域。在其他实施例中，沟槽发射极和沟槽集电极区域可以通过从重掺杂的多晶硅填充的沟槽中的掺杂剂的扩散而形成。

6. 发明申请

US20150380413A1 COMPACT CMOS DEVICE ISOLATION 有权
标题翻译：紧凑的CMOS器件隔离
公开(公告)号：US20150380413A1
公开(公告)日：2015-12-31
申请号：US14320451
申请日：2014-06-30
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Shekar Mallikarjunaswamy
IPC分类号： H01L27/092 , H01L29/06 , H01L21/8238
CPC分类号： H01L29/0646 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L27/0928 , H01L29/1083
摘要： An integrated circuit includes a first well of the first conductivity type formed in a semiconductor layer where the first well housing active devices and being connected to a first well potential, a second well of a second conductivity type formed in the semiconductor layer and encircling the first well where the second well housing active devices and being connected to a second well potential, and a buried layer of the second conductivity type formed under the first well and overlapping at least partially the second well encircling the first well. In an alternate embodiment, instead of the buried layer, the integrated circuit includes a third well of the second conductivity type formed in the semiconductor layer where the third well contains the first well and overlaps at least partially the second well encircling the first well.
摘要翻译：集成电路包括形成在半导体层中的第一导电类型的第一阱，其中第一阱容纳有源器件并连接到第一阱电位，形成在半导体层中的第二导电类型的第二阱并且环绕第一阱电位其中第二阱壳体有源器件并连接到第二阱电位，以及形成在第一阱下面并且至少部分地覆盖环绕第一阱的第二阱的第二导电类型的掩埋层。在替代实施例中，代替埋层，集成电路包括形成在半导体层中的第二导电类型的第三阱，其中第三阱包含第一阱并且至少部分地重叠包围第一阱的第二阱。

7. 发明授权

US10978869B2 USB type-C load switch ESD protection 有权
公开(公告)号：US10978869B2
公开(公告)日：2021-04-13
申请号：US15244996
申请日：2016-08-23
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Shekar Mallikarjunaswamy
IPC分类号： H02H9/04 , H01L23/60 , H01L23/495 , H01L27/02 , H01L25/18 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/49 , H01L29/735 , H01L29/78 , H01L29/861
摘要： A MOSFET and an electrostatic discharge (ESD) protection device on a common chip includes a MOSFET with a source, a gate, and a drain, and an ESD protection device configured to implement a diode function that is biased to prevent current from flowing through the common chip from the source to the drain.

8. 发明授权

US10224411B2 Lateral PNP bipolar transistor with narrow trench emitter 有权
公开(公告)号：US10224411B2
公开(公告)日：2019-03-05
申请号：US15608128
申请日：2017-05-30
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Shekar Mallikarjunaswamy , Francois Hebert
IPC分类号： H01L29/735 , H01L29/66 , H01L29/08 , H01L21/02 , H01L21/225 , H01L21/311 , H01L21/324 , H01L21/762 , H01L29/06
摘要： A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.

9. 发明申请

US20180062386A1 USB TYPE-C LOAD SWITCH ESD PROTECTION 审中-公开
公开(公告)号：US20180062386A1
公开(公告)日：2018-03-01
申请号：US15244996
申请日：2016-08-23
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Shekar Mallikarjunaswamy
IPC分类号： H02H9/04 , H01L29/10 , H01L29/08 , H01L29/423 , H01L29/06 , H01L29/735 , H01L29/861 , H01L29/78 , H01L27/02 , H01L29/49 , H01L25/18
CPC分类号： H02H9/046 , H01L23/49562 , H01L23/49575 , H01L23/60 , H01L25/18 , H01L27/0248 , H01L27/0277 , H01L29/0688 , H01L29/0808 , H01L29/0821 , H01L29/0847 , H01L29/1008 , H01L29/1095 , H01L29/4236 , H01L29/4916 , H01L29/735 , H01L29/78 , H01L29/861 , H01L2224/04042 , H01L2224/16245 , H01L2224/32145 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2924/00012
摘要： A MOSFET and an electrostatic discharge (ESD) protection device on a common chip includes a MOSFET with a source, a gate, and a drain, and an ESD protection device configured to implement a diode function that is biased to prevent current from flowing through the common chip from the source to the drain.

10. 发明申请

US20160358917A1 COMPACT GUARD RING STRUCTURE FOR CMOS INTEGRATED CIRCUITS 审中-公开
标题翻译： CMOS集成电路的紧凑型环形结构
公开(公告)号：US20160358917A1
公开(公告)日：2016-12-08
申请号：US15163512
申请日：2016-05-24
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Shekar Mallikarjunaswamy
IPC分类号： H01L27/092 , H01L29/06
CPC分类号： H01L27/0921 , H01L27/0207 , H01L29/0619 , H01L29/0623 , H01L29/0692 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/7835
摘要： An integrated circuit includes an active device formed in a semiconductor layer of a first conductivity type, a first guard ring of the first conductivity type formed in the semiconductor layer surrounding at least part of the active device; a second guard ring of the second conductivity type formed in the semiconductor layer surrounding the first guard ring and the active device and including comprising alternating first well regions of the first conductivity type and the second well regions of the second conductivity type, the first and second well regions being electrically shorted together and electrically coupled to a ground potential or floating; and a third guard ring of the first conductivity type formed in the semiconductor layer surrounding the second guard ring. The first and third guard rings do not receive direct electrical connection.
摘要翻译：集成电路包括形成在第一导电类型的半导体层中的有源器件，形成在半导体层中的第一导电类型的第一保护环围绕有源器件的至少一部分; 第二导电类型的第二保护环形成在围绕第一保护环和有源器件的半导体层中，并且包括包括交替的第一导电类型的第一阱区和第二导电类型的第二阱区，第一和第二阱区电气短路在一起并电耦合到地电位或浮动; 以及形成在围绕第二保护环的半导体层中的第一导电类型的第三保护环。第一和第三保护环不接收直接电气连接。

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