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    • 1. 发明授权
    • Low-voltage programmable electrical fuses
    • 低压可编程电气保险丝
    • US09006794B1
    • 2015-04-14
    • US14164018
    • 2014-01-24
    • Altera Corporation
    • Shuang XieShankar SinhaCheng-Hsiung Huang
    • H01L23/52H01L23/525H01L21/768
    • H01L23/5256H01L2924/0002H01L2924/00
    • An integrated circuit with electrically programmable fuse circuitry coupled to a programming transistor is provided. The programming transistor may be a metal-oxide-semiconductor transistor that is separated from other circuitry in an integrated circuit substrate with shallow trench isolation. The electrically programmable fuse circuitry may be formed in a second layer above the integrated circuit substrate using a conductive material which may be tungsten-based. This second layer may further include interconnect wires made from the same conductive material. The electrically programmable fuse may be coupled to the programming transistor through vias and routing paths in a fourth layer above the integrated circuit substrate. The routing paths in the fourth layer may be made from a conductive material which may be different than the fuse conductive material used to form the programmable fuse circuitry.
    • 具有耦合到编程晶体管的电可编程熔丝电路的集成电路被提供。 编程晶体管可以是与具有浅沟槽隔离的集成电路衬底中的其它电路分离的金属氧化物半导体晶体管。 电可编程熔丝电路可以使用可以是基于钨的导电材料形成在集成电路衬底上的第二层中。 该第二层还可以包括由相同导电材料制成的互连线。 电可编程熔丝可以通过集成电路基板上方的第四层中的通孔和布线路径耦合到编程晶体管。 第四层中的布线路径可以由导电材料制成,导电材料可以不同于用于形成可编程熔丝电路的熔丝导电材料。
    • 2. 发明授权
    • Electrostatic discharge protection circuitry with reduced capacitance
    • 具有降低电容的静电放电保护电路
    • US09450402B1
    • 2016-09-20
    • US13903901
    • 2013-05-28
    • Altera Corporation
    • Cheng-Hsiung HuangKyle Bowers
    • H02H9/04
    • H02H9/041H01L27/0255H01L27/0277H01L27/0292H02H9/046
    • Integrated circuits with electrostatic discharge (ESD) protection circuitry are provided. Integrated circuits may include input-output pins that are coupled to the ESD protection circuitry. The ESD protection circuitry may include diode circuits, a control circuit, and a power clamp circuit. Each diode circuit may have a first terminal that is coupled to a respective input-output pin and a second terminal that is coupled to a shared ESD control line. The control circuit may supply a boosted voltage onto the control line to reverse bias the diode circuits during normal operation while the power clamp is turned off. During an ESD event, the power clamp may be turned on to sink current from the diode circuits. The power clamp may include a transistor having a substrate that is forward biased to improve transistor drive strength during the ESD event and that is reverse biased to reduce leakage during normal operation.
    • 提供具有静电放电(ESD)保护电路的集成电路。 集成电路可以包括耦合到ESD保护电路的输入 - 输出引脚。 ESD保护电路可以包括二极管电路,控制电路和功率钳位电路。 每个二极管电路可以具有耦合到相应输入输出引脚的第一端子和耦合到共享ESD控制线的第二端子。 控制电路可以在电源钳断开时在正常操作期间将升压的电压提供给控制线以反向偏置二极管电路。 在ESD事件期间,电源钳位可能导通,以从二极管电路吸收电流。 功率钳可以包括晶体管,其具有正向偏置的衬底,以在ESD事件期间提高晶体管驱动强度,并且反向偏置以减少正常操作期间的泄漏。