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1. 发明授权

US08589854B2 Application driven power gating 失效
标题翻译：应用驱动电源门控
公开(公告)号：US08589854B2
公开(公告)日：2013-11-19
申请号：US12835628
申请日：2010-07-13
申请人： Pius Ng , Satish Padmanabhan , Anand Pandurangan , Ananth Durbha , Suresh Kadiyala , Gary Oblock
发明人： Pius Ng , Satish Padmanabhan , Anand Pandurangan , Ananth Durbha , Suresh Kadiyala , Gary Oblock
IPC分类号： G06F11/22
CPC分类号： G06F17/505 , G06F2217/78
摘要： Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了通过接收包括计算机可读代码的定制集成电路的规范并生成计算机可读代码的简档以确定指令使用的方式来管理定制集成电路（IC）设计中的电力的系统和方法; 自动生成针对所述计算机可读代码唯一定制的处理器架构，所述处理器架构具有一个或多个处理块和一个或多个电源域; 基于所述代码简档来确定每个处理块是否需要;以及将每个块分配给所述功率域中的一个; 并根据代码简档对功率域进行选通; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

2. 发明授权

US08423929B2 Intelligent architecture creator 失效
标题翻译：智能建筑创作者
公开(公告)号：US08423929B2
公开(公告)日：2013-04-16
申请号：US12906857
申请日：2010-10-18
申请人： Anand Pandurangan , Pius Ng , Siva Selvaraj , Sanjay Banerjee , Ananth Durbha , Suresh Kadiyala , Satish Padmanabhan
发明人： Anand Pandurangan , Pius Ng , Siva Selvaraj , Sanjay Banerjee , Ananth Durbha , Suresh Kadiyala , Satish Padmanabhan
IPC分类号： G06F17/50
CPC分类号： G06F15/76 , G06F17/505 , G06F2217/68
摘要： Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了系统和方法以自动生成由计算机可读代码描述的定制集成电路（IC）的处理器架构。 IC具有一个或多个时序和硬件限制。该系统从静态简档和计算机可读代码的动态简档中提取定义处理器架构的参数; 通过改变一个或多个参数来迭代地优化处理器架构，直到满足表示为成本函数的所有定时和硬件约束为止; 并将生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

3. 发明授权

US08561005B2 Programmatic auto-convergent method for physical design floorplan aware re-targetable tool suite generation (compiler-in-the-loop) for simultaneous instruction level (software) power optimization and architecture level performance optimization for ASIP design 失效
标题翻译：用于ASIP设计的同步指令级（软件）功耗优化和架构级性能优化的物理设计平面图计划感知可重定向工具套件生成（编译器在循环）的程序化自动收敛方法
公开(公告)号：US08561005B2
公开(公告)日：2013-10-15
申请号：US13452891
申请日：2012-04-22
申请人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
发明人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：系统和方法被公开以通过自动地生成针对每个处理器架构迭代来编译，组合和链接代码的编译器在循环中独特地定制到计算机可读代码的应用特定指令集处理器架构来自动合成定制集成电路所述处理器架构在所述IC上具有执行一个或多个指令的一个或多个处理块; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

4. 发明申请

US20130263067A1 AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION 审中-公开
标题翻译：自动优化集成电路发生器从算法和规范
公开(公告)号：US20130263067A1
公开(公告)日：2013-10-03
申请号：US13626878
申请日：2012-09-25
申请人： Satish Padmanabhan , Pius Ng , Anand Pandurangan , Suresh Kadiyala , Ananth Durbha , Tak Shigihara
发明人： Satish Padmanabhan , Pius Ng , Anand Pandurangan , Suresh Kadiyala , Ananth Durbha , Tak Shigihara
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/5045
摘要： Systems and methods are disclosed to automatically design a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture with programmable processor and one or more co-processors for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了通过接收定制集成电路的规范来自动设计定制集成电路的系统和方法，包括计算机可读代码和定制集成电路上的一个或多个约束; 自动生成具有可编程处理器的计算机体系结构和用于最适合约束的计算机可读代码的一个或多个协处理器; 基于代码简档自动确定指令执行序列，并重新分配或延迟指令序列以在一个或多个处理块上扩展操作以减少热点; 为定制集成电路上的计算机可读代码自动生成相关的测试套件和向量; 并自动合成设计的架构并生成用于半导体制造的定制集成电路的计算机可读描述。

5. 发明授权

US08276107B2 Integrated data model based framework for driving design convergence from architecture optimization to physical design closure 失效
标题翻译：基于集成数据模型的框架，用于从架构优化到物理设计关闭驱动设计融合
公开(公告)号：US08276107B2
公开(公告)日：2012-09-25
申请号：US12906785
申请日：2010-10-18
申请人： Ananth Durbha , Satish Padmanabhan , Pius Ng
发明人： Ananth Durbha , Satish Padmanabhan , Pius Ng
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455 , G06F7/62
CPC分类号： G06F17/5045 , G06F2217/06 , G06F2217/86
摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to computer readable code. The system receives a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed. The look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model.
摘要翻译：公开了系统和方法，以通过在数据模型中编码架构级知识来自动合成定制集成电路，以生成和传递用于物理合成针对计算机可读代码独特定制的芯片规范的新约束。在进行详细的物理合成之后，系统在架构优化期间接收与之前流程中观察到的成本一致的预先成本函数。先行成本函数是从先前的迭代生成的，并通过数据模型提供给后续的迭代。

6. 发明申请

US20120096420A1 INTELLIGENT ARCHITECTURE CREATOR 失效
标题翻译：智能建筑师
公开(公告)号：US20120096420A1
公开(公告)日：2012-04-19
申请号：US12906857
申请日：2010-10-18
申请人： Anand Pandurangan , Pius Ng , Siva Selvaraj , Sanjay Banerjee , Ananth Durbha , Suresh Kadiyala , Satish Padmanabhan
发明人： Anand Pandurangan , Pius Ng , Siva Selvaraj , Sanjay Banerjee , Ananth Durbha , Suresh Kadiyala , Satish Padmanabhan
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F15/76 , G06F17/505 , G06F2217/68
摘要： Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了系统和方法以自动生成由计算机可读代码描述的定制集成电路（IC）的处理器架构。 IC具有一个或多个时序和硬件限制。该系统从静态简档和计算机可读代码的动态简档中提取定义处理器架构的参数; 通过改变一个或多个参数来迭代地优化处理器架构，直到满足表示为成本函数的所有定时和硬件约束为止; 并将生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

7. 发明授权

US08572544B2 Programmatic auto-convergent method for “physical layout power hot-spot” risk aware ASIP architecture customization for performance optimization 失效
标题翻译：用于“物理布局电源热点”的风险识别ASIP架构定制的程序化自动收敛方法进行性能优化
公开(公告)号：US08572544B2
公开(公告)日：2013-10-29
申请号：US13452893
申请日：2012-04-22
申请人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
发明人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Systems and methods are disclosed to automatically method to manage power in a custom integrated circuit (IC) design with a code profile by receiving an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over a plurality of processing blocks to reduce hot spots; applying sub-region weight distributions to estimate power hot-spot locations; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了系统和方法以通过基于代码简档接收指令执行序列并重新分配或延迟指令序列来扩展多个操作或活动来自动地通过代码简档来管理定制集成电路（IC）设计中的电力的方法的加工块来减少热点; 应用子区域权重分布来估计功率热点位置; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

8. 发明申请

US20130111426A1 PROGRAMMATIC AUTO-CONVERGENT METHOD FOR PHYSICAL DESIGN FLOORPLAN AWARE RE-TARGETABLE TOOL SUITE GENERATION (COMPILER-IN-THE-LOOP) FOR SIMULTANEOUS INSTRUCTION LEVEL (SOFTWARE) POWER OPTIMIZATION AND ARCHITECTURE LEVEL PERFORMANCE OPTIMIZATION FOR ASIP DESIGN 失效
标题翻译：用于物理设计FLOORPLAN的可编程自动变换方法用于同步指令级（软件）的功率优化和架构级别性能优化用于ASIP设计的可重定向工具套件生成（编译器）
公开(公告)号：US20130111426A1
公开(公告)日：2013-05-02
申请号：US13452891
申请日：2012-04-22
申请人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
发明人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：系统和方法被公开以通过自动地生成针对每个处理器架构迭代来编译，组合和链接代码的编译器在循环中独特地定制到计算机可读代码的应用特定指令集处理器架构来自动合成定制集成电路所述处理器架构在所述IC上具有执行一个或多个指令的一个或多个处理块; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

9. 发明申请

US20130104097A1 PROGRAMMATIC AUTO-CONVERGENT METHOD FOR "PHYSICAL LAYOUT POWER HOT-SPOT" RISK AWARE ASIP ARCHITECTURE CUSTOMIZATION FOR PERFORMANCE OPTIMIZATION 失效
标题翻译： “物理布局功率热点”的编程自动变换方法风险评估ASIP架构自定义性能优化
公开(公告)号：US20130104097A1
公开(公告)日：2013-04-25
申请号：US13452893
申请日：2012-04-22
申请人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
发明人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Systems and methods are disclosed to automatically method to manage power in a custom integrated circuit (IC) design with a code profile by receiving an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over a plurality of processing blocks to reduce hot spots; applying sub-region weight distributions to estimate power hot-spot locations; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了系统和方法以通过基于代码简档接收指令执行序列并重新分配或延迟指令序列来扩展多个操作或活动来自动地通过代码简档来管理定制集成电路（IC）设计中的电力的方法的加工块来减少热点; 应用子区域权重分布来估计功率热点位置; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

10. 发明申请

US20120096417A1 INTEGRATED DATA MODEL BASED FRAMEWORK FOR DRIVING DESIGN CONVERGENCE FROM ARCHITECTURE OPTIMIZATION TO PHYSICAL DESIGN CLOSURE 失效
标题翻译：基于数据模型的集成框架，用于从建筑优化到物理设计关闭的设计合并
公开(公告)号：US20120096417A1
公开(公告)日：2012-04-19
申请号：US12906785
申请日：2010-10-18
申请人： Ananth Durbha , Pius Ng , Satish Padmanabhan
发明人： Ananth Durbha , Pius Ng , Satish Padmanabhan
IPC分类号： G06F17/50 , G06F9/455 , G06F9/45
CPC分类号： G06F17/5045 , G06F2217/06 , G06F2217/86
摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to the computer readable code; receiving a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed, wherein the look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model; automatically translating information available at one optimization point into a constraint for another optimization point invoked at a different place in the design flow using the data model; and synthesizing a computer readable description of the chip specification into the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了系统和方法，通过接收包括计算机可读代码和定制集成电路上的一个或多个约束的定制集成电路的规范来自动地合成定制集成电路; 编码数据模型中的架构级知识，以生成和传递新的约束，用于物理合成芯片规范，该芯片规范独特地定制到计算机可读代码; 在进行详细的物理合成之后，在结构优化期间接收与之前的流程中观察到的成本一致的先行成本函数，其中，先行成本函数是从先前的迭代生成的并提供给通过数据模型的后续迭代; 将在一个优化点处可用的信息自动翻译成使用数据模型在设计流程中不同位置调用的另一优化点的约束; 以及将芯片规格的计算机可读描述合成到用于半导体制造的定制集成电路中。

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