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1. 发明授权

US09886275B1 Multi-core processor using three dimensional integration 有权
公开(公告)号：US09886275B1
公开(公告)日：2018-02-06
申请号：US14508027
申请日：2014-10-07
申请人： Andrew Carlson , Matthew Mattina
发明人： Andrew Carlson , Matthew Mattina
IPC分类号： H01L25/00 , G06F9/30 , H01L25/065 , G06F13/00
CPC分类号： G06F13/00 , G06F9/30098 , G06F15/76 , G06F15/7807 , H01L25/0657 , H01L2225/06513 , H01L2225/06541
摘要： Techniques for interconnects structures for a multi-core processor including at least two multi-core integrated circuits include forming at least two multi-core integrated circuits each on a respective substrate into a stack, disposing connections through the stack between a circuit of a first one of the at least two multi-core integrated circuits and a circuit of a second, different one of the at least two multi-core integrated circuits, the integrated circuits arranged in the stack with connections of the first one connected to a receiving pad of the second one.

2. 发明授权

US09479431B1 Route prediction in packet switched networks 有权
公开(公告)号：US09479431B1
公开(公告)日：2016-10-25
申请号：US14854286
申请日：2015-09-15
申请人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
发明人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
IPC分类号： H04L12/28 , H04L12/703 , H04L12/751 , H04L12/707 , H04L12/933
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Communicating among nodes in a network includes: sending a packet from an origin node to a destination node over a route including plural nodes. At each node in the route, routing of the packet is initiated according to a predicted path concurrently with verifying the correctness of the predicted path based on analyzing route information in the packet. In response to results of verifying the correctness of the predicted path, the routing of the packet is completed according to the predicted path or initiating a routing of the packet according to an actual path based on the route information in the packet.

3. 发明授权

US09135215B1 Route prediction in packet switched networks 有权
标题翻译：分组交换网络中的路由预测
公开(公告)号：US09135215B1
公开(公告)日：2015-09-15
申请号：US12886163
申请日：2010-09-20
申请人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
发明人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
IPC分类号： H04L12/28 , G06F15/80 , H04L12/911
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Communicating among nodes in a network includes: sending a packet from an origin node to a destination node over a route including plural nodes. At each node in the route, routing of the packet is initiated according to a predicted path concurrently with verifying the correctness of the predicted path based on analyzing route information in the packet. In response to results of verifying the correctness of the predicted path, the routing of the packet is completed according to the predicted path or initiating a routing of the packet according to an actual path based on the route information in the packet.
摘要翻译：在网络中的节点之间进行通信包括：通过包括多个节点的路由将分组从原始节点发送到目的地节点。在路由中的每个节点，基于分组中的路由信息，根据预测路径同时发起分组的路由，同时验证预测路径的正确性。响应于验证预测路径的正确性的结果，根据预测路径完成分组的路由，或者基于分组中的路由信息根据实际路径发起分组的路由。

4. 发明授权

US08934347B1 Low latency dynamic route selection 有权
标题翻译：低延迟动态路由选择
公开(公告)号：US08934347B1
公开(公告)日：2015-01-13
申请号：US12886346
申请日：2010-09-20
申请人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
发明人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
IPC分类号： G06F11/00
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Communicating among cores in a computing system comprising a plurality of cores, each core comprising a processor and a switch, includes: routing a packet from a core or from a device coupled to at least one core to a destination over a route including one or more cores, with an order of dimensions associated with the route being selected dynamically upon construction of the packet; routing the packet to a first core in the route over the first selected dimension; and routing the packet from the first core to the destination over the second dimension.
摘要翻译：在包括多个核心的计算系统中的核心之间进行通信，每个核心包括处理器和交换机，包括：通过包括一个或多个路由的路由将来自核心或从耦合到至少一个核心的设备的分组路由到目的地核心，在构建分组时具有与路线相关联的维度顺序被动态地选择; 将所述分组路由到所述路由中的所述第一选定维度上的第一核心; 并且在第二维度上将分组从第一核心路由到目的地。

5. 发明授权

US08560780B1 Caching in multicore and multiprocessor architectures 有权
标题翻译：在多核和多处理器架构中进行缓存
公开(公告)号：US08560780B1
公开(公告)日：2013-10-15
申请号：US13553884
申请日：2012-07-20
申请人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
发明人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0817
摘要： A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.
摘要翻译：多核处理器包括多个高速缓存存储器和多个处理器核心，每个处理器核心与高速缓冲存储器之一相关联。至少一些高速缓存存储器中的每一个被配置为保持高速缓冲存储器的至少一部分，其中每个高速缓存行被动态地管理为相关联的处理器核心的本地或在多个处理器核心之间共享。

6. 发明授权

US07747897B2 Method and apparatus for lockstep processing on a fixed-latency interconnect 有权
标题翻译：在固定延迟互连上进行锁步处理的方法和装置
公开(公告)号：US07747897B2
公开(公告)日：2010-06-29
申请号：US11282213
申请日：2005-11-18
申请人： Paul B. Racunas , Matthew Mattina , George Z. Chrysos , Shubhendu S. Mukherjee
发明人： Paul B. Racunas , Matthew Mattina , George Z. Chrysos , Shubhendu S. Mukherjee
IPC分类号： G06F11/00 , G06F17/00 , G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F11/1683 , G06F11/1637
摘要： Methods of operating two or more devices in lockstep by generating requests at each device, comparing the requests, and forwarding matching requests to a servicing node are described and claimed. A redundant execution system using the methods is also described and claimed.
摘要翻译：描述并要求保护在每个设备上生成请求，比较请求以及将匹配请求转发到服务节点的锁步骤中的两个或多个设备的操作方法。还描述并声明了使用该方法的冗余执行系统。

7. 发明授权

US07624236B2 Predictive early write-back of owned cache blocks in a shared memory computer system 有权
标题翻译：在共享内存计算机系统中预测所有缓存块的早期回写
公开(公告)号：US07624236B2
公开(公告)日：2009-11-24
申请号：US11023882
申请日：2004-12-27
申请人： George Z. Chrysos , Matthew Mattina
发明人： George Z. Chrysos , Matthew Mattina
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/084 , G06F12/0804 , G06F12/0811 , G06F12/0815
摘要： A method for predicting early write back of owned cache blocks in a shared memory computer system. This invention enables the system to predict which written blocks may be more likely to be requested by another CPU and the owning CPU will write those blocks back to memory as soon as possible after updating the data in the block. If another processor is requesting the data, this can reduce the latency to get that data, reducing synchronization overhead, and increasing the throughput of parallel programs.
摘要翻译：一种用于预测共享存储器计算机系统中所拥有的高速缓存块的早期回写的方法。本发明使得系统能够预测哪些写入块可能被另一个CPU更可能请求，并且拥有的CPU将在更新块中的数据之后尽快将这些块写回存储器。如果另一个处理器正在请求数据，则可以减少获取该数据的延迟，减少同步开销，并增加并行程序的吞吐量。

8. 发明申请

US20070143550A1 Per-set relaxation of cache inclusion 审中-公开
标题翻译：缓存包容的放松
公开(公告)号：US20070143550A1
公开(公告)日：2007-06-21
申请号：US11313114
申请日：2005-12-19
申请人： Ravi Rajwar , Matthew Mattina
发明人： Ravi Rajwar , Matthew Mattina
IPC分类号： G06F13/28
CPC分类号： G06F12/0811 , G06F12/084
摘要： A multi-core processor includes a plurality of processors and a shared cache. Cache control logic implements an inclusive cache scheme among the shared cache and the local caches for the processors. Counters are maintained to track instances, per set, when a processor chooses to delay eviction from the local cache. While the counter indicates that one or more delayed evictions are pending for a set, the cache control logic treats the set as non-inclusive, broadcasting foreign snoops to all of the local caches, regardless of whether the snoop hits in the shared cache. Other embodiments are also described and claimed.
摘要翻译：多核处理器包括多个处理器和共享高速缓存。缓存控制逻辑在共享高速缓存和处理器的本地高速缓存之间实现包容性高速缓存方案。当处理器选择延迟从本地缓存驱逐时，计数器被维护以跟踪每集的实例。虽然计数器指示一个或多个延迟的撤离正在等待一组，但是高速缓存控制逻辑将该集合视为非包容性，将广播外部侦听广播到所有本地高速缓存，而不管窥探者是否在共享高速缓存中命中。还描述和要求保护其他实施例。

9. 发明授权

US10073778B1 Caching in multicore and multiprocessor architectures 有权
公开(公告)号：US10073778B1
公开(公告)日：2018-09-11
申请号：US15368947
申请日：2016-12-05
申请人： Ian Rudolf Bratt , Matthew Mattina
发明人： Anant Agarwal , Ian Rudolf Bratt , Matthew Mattina
IPC分类号： G06F12/08 , G06F12/0817 , G06F12/0811 , G06F12/084 , G06F12/1081 , G06F13/40
CPC分类号： G06F12/0817 , G06F12/0811 , G06F12/0815 , G06F12/084 , G06F12/1081 , G06F13/4022 , G06F2212/60 , G06F2212/621
摘要： A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.

10. 发明授权

US09639487B1 Managing cache memory in a parallel processing environment 有权
公开(公告)号：US09639487B1
公开(公告)日：2017-05-02
申请号：US15083408
申请日：2016-03-29
申请人： Matthew Mattina
发明人： David M Wentzlaff , Matthew Mattina , Anant Agarwal
IPC分类号： G06F12/10 , G06F13/24 , G06F12/0815 , G06F12/1045 , G06F13/16 , G06F13/40
CPC分类号： G06F13/24 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/1027 , G06F12/1045 , G06F13/16 , G06F13/4022 , G06F2212/60 , G06F2212/621 , G06F2212/682 , H04L49/109
摘要： An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.

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