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1. 发明授权

US09564901B1 Self-timed dynamic level shifter with falling edge generator 有权
标题翻译：具有下降沿发生器的自定时动态电平转换器
公开(公告)号：US09564901B1
公开(公告)日：2017-02-07
申请号：US14972754
申请日：2015-12-17
申请人： Apple Inc.
发明人： Daniel C. Chow , Kenneth W. Jones , William R. Weier
IPC分类号： H03K19/0185 , H03K3/356 , H03K5/156
CPC分类号： H03K19/01855 , H03K5/05 , H03K5/1565
摘要： A clock circuit configured to generate a falling edge independently of an input clock signal is disclosed. In one embodiment, a clock circuit includes an input circuit coupled to receive an input clock signal. A corresponding first clock signal is provided on a first clock node, while a second clock signal that is a delayed version of the first is provided on a second clock signal. The clock circuit may generate an output clock signal based on the first and second clock signals and a feedback signal received from a functional circuit coupled to receive the output clock signal. The rising edge of the output clock signal is generated dependent upon when the rising edge of the input clock signal is received. The falling edge of the output clock signal is generated by the clock circuit independently of when the falling edge of the input clock signal is received.
摘要翻译：公开了一种配置成独立于输入时钟信号产生下降沿的时钟电路。在一个实施例中，时钟电路包括耦合以接收输入时钟信号的输入电路。在第一时钟节点上提供对应的第一时钟信号，而在第二时钟信号上提供作为第一时钟信号的延迟版本的第二时钟信号。时钟电路可以基于第一和第二时钟信号产生输出时钟信号，以及从耦合以接收输出时钟信号的功能电路接收的反馈信号。输出时钟信号的上升沿取决于输入时钟信号的上升沿何时被接收。输出时钟信号的下降沿由时钟电路产生，独立于接收到输入时钟信号的下降沿时。

2. 发明申请

US20140016392A1 Memory Having Isolation Units For Isolating Storage Arrays From A Shared I/O During Retention Mode Operation 有权
标题翻译：具有隔离单元的存储器，用于在保留模式操作期间从共享I / O隔离存储阵列
公开(公告)号：US20140016392A1
公开(公告)日：2014-01-16
申请号：US14029989
申请日：2013-09-18
申请人： Apple Inc.
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/06 , G11C11/4091 , G11C2207/002
摘要： A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.
摘要翻译：存储器包括在多个存储阵列之间共享的I / O单元。共享I / O单元提供阵列的输出数据。存储器包括连接在每个存储阵列和共享I / O单元之间的隔离单元。此外，每个存储阵列和共享I / O单元可以通过例如电源门控电路连接到单独的开关电压域。如果一个或多个存储阵列被置于保持或低电压模式，则耦合到受影响的存储阵列的隔离单元可以被配置为将这些存储阵列的位线与共享的I / O数据路径隔离开来。

3. 发明授权

US08767495B2 Memory having isolation units for isolating storage arrays from a shared I/O during retention mode operation 有权
标题翻译：存储器具有隔离单元，用于在保持模式操作期间将存储阵列与共享I / O隔离
公开(公告)号：US08767495B2
公开(公告)日：2014-07-01
申请号：US14029989
申请日：2013-09-18
申请人： Apple Inc.
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/02
CPC分类号： G11C5/063 , G11C7/06 , G11C11/4091 , G11C2207/002
摘要： A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.
摘要翻译：存储器包括在多个存储阵列之间共享的I / O单元。共享I / O单元提供阵列的输出数据。存储器包括连接在每个存储阵列和共享I / O单元之间的隔离单元。此外，每个存储阵列和共享I / O单元可以通过例如电源门控电路连接到单独的开关电压域。如果一个或多个存储阵列被置于保持或低电压模式，则耦合到受影响的存储阵列的隔离单元可以被配置为将这些存储阵列的位线与共享的I / O数据路径隔离开来。

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