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1. 发明申请

US20190173472A1 CLOCK GATING CIRCUIT 审中-公开
公开(公告)号：US20190173472A1
公开(公告)日：2019-06-06
申请号：US16259631
申请日：2019-01-28
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Ah-Reum KIM , Hyun LEE , Min-su KIM
IPC分类号： H03K19/0185 , H03K3/356 , H03K3/037 , H03K19/00 , H03K3/012
CPC分类号： H03K19/01855 , H03K3/012 , H03K3/037 , H03K3/356104 , H03K3/356191 , H03K19/0013
摘要： Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

2. 发明授权

US09948303B2 High speed voltage level shifter 有权
公开(公告)号：US09948303B2
公开(公告)日：2018-04-17
申请号：US15367751
申请日：2016-12-02
申请人： QUALCOMM Incorporated
发明人： Venkat Narayanan , Rakesh Vattikonda , De Lu , Ramaprasath Vilangudipitchai , Samrat Sinharoy , Rui Chen
IPC分类号： H03L5/00 , H03K19/0185 , H03K19/00
CPC分类号： H03K19/018521 , H03K3/356121 , H03K3/356191 , H03K19/0013 , H03K19/01855 , H03K19/0963
摘要： In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.

3. 发明授权

US09871523B2 High speed level translator 有权
公开(公告)号：US09871523B2
公开(公告)日：2018-01-16
申请号：US15244829
申请日：2016-08-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John A. Fifield
IPC分类号： H03L5/00 , H03K19/0185 , H03K19/017 , H03K19/0944
CPC分类号： H03K19/01855 , H03K19/01742 , H03K19/0944
摘要： A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

4. 发明授权

US09584126B2 Bias circuit for a switched capacitor level shifter 有权
标题翻译：用于开关电容器电平移位器的偏置电路
公开(公告)号：US09584126B2
公开(公告)日：2017-02-28
申请号：US14710515
申请日：2015-05-12
申请人： Atieva, Inc.
发明人： Richard J. Biskup
IPC分类号： H03K19/0185 , G01R19/00 , H03K17/16 , G01R19/165
CPC分类号： H03K19/01855 , G01R19/0084 , G01R19/16542 , H03K17/162 , H03K19/018521
摘要： A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter. The first voltage clamp is configured to couple to a control terminal of the switch and limit a voltage of the control terminal relative to the first terminal to within a first clamping range. The circuit includes a second voltage clamp coupled to an input terminal of the switch control circuit. The second voltage clamp is configured to couple to the control terminal of the switch. The second voltage clamp is further configured to reduce a level of a control voltage coupled to the second voltage clamp. The circuit includes a bias device configured to couple to the control terminal of the switch and to impress a biasing voltage to the control terminal.
摘要翻译：提供了一种抗噪声开关控制电路。电路包括配置成耦合到开关的第一端子的低通滤波器和耦合到低通滤波器的第一电压钳位。第一电压钳被配置为耦合到开关的控制端子，并且将控制端子相对于第一端子的电压限制在第一钳位范围内。电路包括耦合到开关控制电路的输入端的第二电压钳位。第二电压钳被配置为耦合到开关的控制端。第二电压钳还被配置为降低耦合到第二电压钳的控制电压的电平。电路包括被配置为耦合到开关的控制端子并且向控制端子施加偏置电压的偏置装置。

5. 发明授权

US09564901B1 Self-timed dynamic level shifter with falling edge generator 有权
标题翻译：具有下降沿发生器的自定时动态电平转换器
公开(公告)号：US09564901B1
公开(公告)日：2017-02-07
申请号：US14972754
申请日：2015-12-17
申请人： Apple Inc.
发明人： Daniel C. Chow , Kenneth W. Jones , William R. Weier
IPC分类号： H03K19/0185 , H03K3/356 , H03K5/156
CPC分类号： H03K19/01855 , H03K5/05 , H03K5/1565
摘要： A clock circuit configured to generate a falling edge independently of an input clock signal is disclosed. In one embodiment, a clock circuit includes an input circuit coupled to receive an input clock signal. A corresponding first clock signal is provided on a first clock node, while a second clock signal that is a delayed version of the first is provided on a second clock signal. The clock circuit may generate an output clock signal based on the first and second clock signals and a feedback signal received from a functional circuit coupled to receive the output clock signal. The rising edge of the output clock signal is generated dependent upon when the rising edge of the input clock signal is received. The falling edge of the output clock signal is generated by the clock circuit independently of when the falling edge of the input clock signal is received.
摘要翻译：公开了一种配置成独立于输入时钟信号产生下降沿的时钟电路。在一个实施例中，时钟电路包括耦合以接收输入时钟信号的输入电路。在第一时钟节点上提供对应的第一时钟信号，而在第二时钟信号上提供作为第一时钟信号的延迟版本的第二时钟信号。时钟电路可以基于第一和第二时钟信号产生输出时钟信号，以及从耦合以接收输出时钟信号的功能电路接收的反馈信号。输出时钟信号的上升沿取决于输入时钟信号的上升沿何时被接收。输出时钟信号的下降沿由时钟电路产生，独立于接收到输入时钟信号的下降沿时。

6. 发明申请

US20170005660A1 MULTIPLEXER AND LATCH SYSTEM 审中-公开
标题翻译：多路复用器和锁存系统
公开(公告)号：US20170005660A1
公开(公告)日：2017-01-05
申请号：US14755999
申请日：2015-06-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Hyunsung HONG
IPC分类号： H03K19/0185 , H03K17/693
CPC分类号： H03K19/01855 , H03K17/693
摘要： A memory includes a clock generator and a multiplexing latch circuit. The clock generator is configured to generate a first latching clock signal and a second latching clock signal based on a multiplexing select signal and a clock signal, and to transmit the first latching clock signal and the second latching clock signal. The multiplexing latch circuit is configured to select the first data or the second data based on the first latching clock signal and the second latching clock signal, and to store and output the selected data.
摘要翻译：存储器包括时钟发生器和复用锁存电路。时钟发生器被配置为基于复用选择信号和时钟信号产生第一锁存时钟信号和第二锁存时钟信号，并且发送第一锁存时钟信号和第二锁存时钟信号。复用锁存电路被配置为基于第一锁存时钟信号和第二锁存时钟信号来选择第一数据或第二数据，并且存储和输出所选择的数据。

7. 发明授权

US09503090B2 High speed level translator 有权
标题翻译：高速翻译器
公开(公告)号：US09503090B2
公开(公告)日：2016-11-22
申请号：US14463136
申请日：2014-08-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John A. Fifield
IPC分类号： H03L5/00 , H03K19/017 , H03K19/0185 , H03K19/0944
CPC分类号： H03K19/01855 , H03K19/01742 , H03K19/0944
摘要： A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.
摘要翻译：公开了使用薄氧化物场效应晶体管（FET）和使用方法的高速VPP电平转换器电路。电平转换器包括电阻分压器和与电阻分压器并联的单触发电路。单触发电路导通以辅助从第一状态转换到第二状态，并且在从第二状态到第一状态的转变期间是不导通的。

8. 发明授权

US09490805B2 Low power driver with programmable output impedance 有权
标题翻译：具有可编程输出阻抗的低功耗驱动器
公开(公告)号：US09490805B2
公开(公告)日：2016-11-08
申请号：US14475544
申请日：2014-09-02
申请人： Integrated Device Technology, Inc.
发明人： John Hsu
IPC分类号： H03K19/00 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/0005 , H03K19/00361 , H03K19/01855 , H03K19/018585
摘要： A programmable low power driver permits an output impedance of the driver to be programmed. Programmability permits the driver output impedance to match an impedance of a transmission line that is connected thereto. The low power driver includes a first driver output and a plurality of driver legs. The programmable low power driver is configured to electrically couple one or more driver legs of the plurality of driver legs to the first driver output to establish an output impedance for the driver.
摘要翻译：可编程低功率驱动器允许对驱动器的输出阻抗进行编程。可编程性允许驱动器输出阻抗匹配与其连接的传输线的阻抗。低功率驱动器包括第一驱动器输出和多个驱动器脚。可编程低功率驱动器被配置为将多个驱动器支路中的一个或多个驱动器支路电耦合到第一驱动器输出以建立用于驱动器的输出阻抗。

9. 发明申请

US20160098061A1 SCALABLE 2.5D INTERFACE ARCHITECTURE 有权
标题翻译：可扩展的2.5D接口架构
公开(公告)号：US20160098061A1
公开(公告)日：2016-04-07
申请号：US14692133
申请日：2015-04-21
申请人： Altera Corporation
发明人： Chee Hak Teh
IPC分类号： G06F1/08 , H03K19/0185 , G06F17/50
CPC分类号： H03K19/01855 , G06F17/5068
摘要： Systems and methods for interface block. The interface block includes input/output modules distributed along the interface block and a mid-stack module interspersed within the input/output modules. The input/output modules include at least one data module and at least one command module. At least one of the input/output modules is shared by an adjacent pair of channels. Each of the input/output modules is configured to interface with a memory device via a silicon interposer or equivalent. The mid-stack module is in communication with the input/output modules via programmable logic circuitry. The mid-stack module may include independent clock quadrants. Each clock quadrant is configured to operate at different phases where each phase is aligned to a respective core clock.
摘要翻译：接口块的系统和方法。接口块包括沿着接口块分布的输入/输出模块和散布在输入/输出模块内的中间堆栈模块。输入/输出模块包括至少一个数据模块和至少一个命令模块。至少一个输入/输出模块由相邻的通道对共享。每个输入/输出模块被配置为经由硅插入器或等同物与存储器件接口。中间堆栈模块通过可编程逻辑电路与输入/输出模块通信。中间堆叠模块可以包括独立的时钟象限。每个时钟象限被配置为在不同的相位工作，其中每个相位与相应的核心时钟对准。

10. 发明申请

US20160056822A1 HIGH SPEED LEVEL TRANSLATOR 有权
标题翻译：高速电平转换器
公开(公告)号：US20160056822A1
公开(公告)日：2016-02-25
申请号：US14463136
申请日：2014-08-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John A. FIFIELD
IPC分类号： H03K19/017 , H03K19/0944 , H03K19/0185
CPC分类号： H03K19/01855 , H03K19/01742 , H03K19/0944
摘要： A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.
摘要翻译：公开了使用薄氧化物场效应晶体管（FET）和使用方法的高速VPP电平转换器电路。电平转换器包括电阻分压器和与电阻分压器并联的单触发电路。单触发电路导通以辅助从第一状态转换到第二状态，并且在从第二状态到第一状态的转变期间是不导通的。

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