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1. 发明授权

US11200062B2 History file for previous register mapping storage and last reference indication 有权
公开(公告)号：US11200062B2
公开(公告)日：2021-12-14
申请号：US16551208
申请日：2019-08-26
申请人： Apple Inc.
发明人： Deepankar Duggal , Conrado Blasco , Muawya M. Al-Otoom , Richard F. Russo
IPC分类号： G06F9/38
摘要： Systems, apparatuses, and methods for implementing a physical register last reference scheme are described. A system includes a processor with a mapper, history file, and freelist. When an entry in the mapper is updated with a new architectural register-to-physical register mapping, the processor creates a new history file entry for the given instruction that caused the update. The processor also searches the mapper to determine if the old physical register that was previously stored in the mapper entry is referenced by any other mapper entries. If there are no other mapper entries that reference this old physical register, then a last reference indicator is stored in the new history file entry. When the given instruction retires, the processor checks the last reference indicator in the history file entry to determine whether the old physical register can be returned to the freelist of available physical registers.

2. 发明授权

US09940262B2 Immediate branch recode that handles aliasing 有权
公开(公告)号：US09940262B2
公开(公告)日：2018-04-10
申请号：US14491149
申请日：2014-09-19
申请人： Apple Inc.
发明人： Shyam Sundar , Richard F. Russo , Ronald P. Hall , Conrado Blasco
IPC分类号： G06F12/1045 , G06F12/0875 , G06F9/38 , G06F9/32 , G06F12/1027
CPC分类号： G06F12/1045 , G06F9/324 , G06F9/3804 , G06F9/382 , G06F12/0875 , G06F12/1027 , G06F2212/452 , G06F2212/684
摘要： A system and method for efficiently indicating branch target addresses. A semiconductor chip predecodes instructions of a computer program prior to installing the instructions in an instruction cache. In response to determining a particular instruction is a control flow instruction with a displacement relative to a program counter address (PC), the chip replaces a portion of the PC relative displacement in the particular instruction with a subset of a target address. The subset of the target address is an untranslated physical subset of the full target address. When the recoded particular instruction is fetched and decoded, the remaining portion of the PC relative displacement is added to a virtual portion of the PC used to fetch the particular instruction. The result is concatenated with the portion of the target address embedded in the fetched particular instruction to form a full target address.

3. 发明申请

US20160085550A1 IMMEDIATE BRANCH RECODE THAT HANDLES ALIASING 有权
标题翻译：立即分配掌握手柄
公开(公告)号：US20160085550A1
公开(公告)日：2016-03-24
申请号：US14491149
申请日：2014-09-19
申请人： Apple Inc.
发明人： Shyam Sundar , Richard F. Russo , Ronald P. Hall , Conrado Blasco
IPC分类号： G06F9/30 , G06F12/08 , G06F12/10 , G06F9/38
CPC分类号： G06F12/1045 , G06F9/324 , G06F9/3804 , G06F9/382 , G06F12/0875 , G06F12/1027 , G06F2212/452 , G06F2212/684
摘要： A system and method for efficiently indicating branch target addresses. A semiconductor chip predecodes instructions of a computer program prior to installing the instructions in an instruction cache. In response to determining a particular instruction is a control flow instruction with a displacement relative to a program counter address (PC), the chip replaces a portion of the PC relative displacement in the particular instruction with a subset of a target address. The subset of the target address is an untranslated physical subset of the full target address. When the recoded particular instruction is fetched and decoded, the remaining portion of the PC relative displacement is added to a virtual portion of the PC used to fetch the particular instruction. The result is concatenated with the portion of the target address embedded in the fetched particular instruction to form a full target address.
摘要翻译：一种有效指示分支目标地址的系统和方法。在将指令安装到指令高速缓存之前，半导体芯片预先对计算机程序的指令进行解码。响应于确定特定指令是具有相对于程序计数器地址（PC）的位移的控制流程指令，芯片用目标地址的子集替换特定指令中的PC相对位移的一部分。目标地址的子集是完整目标地址的非翻译物理子集。当重新编码的特定指令被取出和解码时，PC相对位移的剩余部分被添加到用于获取特定指令的PC的虚拟部分。结果与嵌入在获取的特定指令中的目标地址的部分连接以形成完整的目标地址。

4. 发明申请

US20220083484A1 Scalable Interrupts 有权
公开(公告)号：US20220083484A1
公开(公告)日：2022-03-17
申请号：US17246311
申请日：2021-04-30
申请人： Apple Inc.
发明人： Jeffrey E. Gonion , Charles E. Tucker , Tal Kuzi , Richard F. Russo , Mridul Agarwal , Christopher M. Tsay , Gideon N. Levinsky , Shih-Chieh Wen
IPC分类号： G06F13/24 , G06F1/26
摘要： An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

5. 发明授权

US10401945B2 Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture 有权
公开(公告)号：US10401945B2
公开(公告)日：2019-09-03
申请号：US15935274
申请日：2018-03-26
申请人： Apple Inc.
发明人： David J. Williamson , Gerard R. Williams, III , James N. Hardage, Jr. , Richard F. Russo
IPC分类号： G06F1/32 , G06F1/3293 , G06F1/3234 , G06F1/3287 , G06F9/50
摘要： In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

6. 发明授权

US09958932B2 Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture 有权
公开(公告)号：US09958932B2
公开(公告)日：2018-05-01
申请号：US14548912
申请日：2014-11-20
申请人： Apple Inc.
发明人： David J. Williamson , Gerard R. Williams, III , James N. Hardage, Jr. , Richard F. Russo
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/3293 , G06F1/3275 , G06F1/3287 , G06F9/5094 , Y02D10/122 , Y02D10/171
摘要： In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

7. 发明授权

US09952863B1 Program counter capturing 有权
公开(公告)号：US09952863B1
公开(公告)日：2018-04-24
申请号：US14842421
申请日：2015-09-01
申请人： Apple Inc.
发明人： Conrado Blasco , Deepankar Duggal , Richard F. Russo
IPC分类号： G06F9/44 , G06F9/45 , G06F9/445 , G06F9/30 , G06F9/38 , G06F9/32
CPC分类号： G06F9/3005 , G06F9/30079 , G06F9/30145 , G06F9/327 , G06F9/3855 , G06F11/30
摘要： Techniques are disclosed relating to capturing information related to instructions executing on in a processor. In one embodiment, an integrated circuit is disclosed that includes an execution pipeline configured to execute a sequence of instructions. The integrated circuit includes monitoring circuitry configured to monitor the execution pipeline for occurrences of an event associated with the sequence of instructions, and in response to detecting a particular number of occurrences of the event, capture a value of a program counter corresponding to an instruction of the sequence of instructions that is associated with an occurrence of the event. The monitoring circuitry stores the captured value of the program counter in a distinct capture register and signals an interrupt indicating that the captured value of the program counter is retrievable from the capture register. In some embodiments, a debugging application may retrieve the value and present it to a developer attempting perform code profiling.

8. 发明申请

US20210064376A1 LAST PHYSICAL REGISTER REFERENCE SCHEME 有权
公开(公告)号：US20210064376A1
公开(公告)日：2021-03-04
申请号：US16551208
申请日：2019-08-26
申请人： Apple Inc.
发明人： Deepankar Duggal , Conrado Blasco , Muawya M. Al-Otoom , Richard F. Russo
IPC分类号： G06F9/38
摘要： Systems, apparatuses, and methods for implementing a physical register last reference scheme are described. A system includes a processor with a mapper, history file, and freelist. When an entry in the mapper is updated with a new architectural register-to-physical register mapping, the processor creates a new history file entry for the given instruction that caused the update. The processor also searches the mapper to determine if the old physical register that was previously stored in the mapper entry is referenced by any other mapper entries. If there are no other mapper entries that reference this old physical register, then a last reference indicator is stored in the new history file entry. When the given instruction retires, the processor checks the last reference indicator in the history file entry to determine whether the old physical register can be returned to the freelist of available physical registers.

9. 发明申请

US20180307297A1 ARCHITECTED STATE RETENTION 审中-公开
公开(公告)号：US20180307297A1
公开(公告)日：2018-10-25
申请号：US15496290
申请日：2017-04-25
申请人： Apple Inc.
发明人： Bernard Joseph Semeria , John H. Mylius , Pradeep Kanapathipillai , Richard F. Russo , Shih-Chieh Wen , Richard H. Larson
IPC分类号： G06F1/32 , G06F9/38 , G06F3/06
CPC分类号： G06F1/3287 , G06F1/3206 , G06F1/3228 , G06F1/3296 , G06F3/0619 , G06F3/0625 , G06F3/065 , G06F3/067 , G06F9/3802
摘要： Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.

10. 发明申请

US20170068575A1 Hardware Migration between Dissimilar Cores 有权
标题翻译：不同核心之间的硬件迁移
公开(公告)号：US20170068575A1
公开(公告)日：2017-03-09
申请号：US14844212
申请日：2015-09-03
申请人： Apple Inc.
发明人： James N. Hardage, JR. , Daniel U. Becker , Christopher M. Tsay , Richard F. Russo , Shih-Chieh R. Wen , Richard H. Larson
IPC分类号： G06F9/50 , G06F9/30 , G06F9/38 , G06F12/08
CPC分类号： G06F9/5088 , G06F9/30101 , G06F9/3828 , G06F12/0813 , G06F12/084 , G06F2212/1028 , G06F2212/314 , Y02D10/13
摘要： In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.
摘要翻译：在一个实施例中，集成电路可以包括一个或多个处理器。每个处理器可以包括多个处理器核心，并且每个核心具有不同的设计/实现和性能水平。处理器可以支持多种处理器状态（PState）。每个PState可以指定工作点（例如，电源电压幅度和时钟频率的组合），并且每个PState可以映射到处理器核心之一。在运行期间，其中一个核心是活动的：当前PState映射到的核心。如果选择新的PState并将其映射到不同的核心，则处理器可以自动地将处理器状态切换到新选择的核心，并且可以在该核心上开始执行。可以使用专用寄存器（SPR）互连来执行上下文切换。给定处理器中的每个处理器核心可以耦合到SPR互连以允许访问外部SPR。

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