专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09348658B1 Technologies for efficient synchronization barriers with work stealing support 有权
标题翻译：技术的高效同步障碍与工作窃取支持
公开(公告)号：US09348658B1
公开(公告)日：2016-05-24
申请号：US14568831
申请日：2014-12-12
申请人： Arch D. Robison , Alejandro Duran Gonzalez
发明人： Arch D. Robison , Alejandro Duran Gonzalez
IPC分类号： G06F9/46 , G06F9/52
CPC分类号： G06F9/522 , G06F9/4856
摘要： Technologies for multithreaded synchronization and work stealing include a computing device executing two or more threads in a thread team. A thread executes all of the tasks in its task queue and then exchanges its associated task stolen flag value with false and stores that value in a temporary flag. Subsequently, the thread enters a basic synchronization barrier. The computing device performs a logical-OR reduction over the temporary flags of the thread team to produce a reduction value. While waiting for other threads of the thread team to enter the barrier, the thread may steal a task from a victim thread and set the task stolen flag of the victim thread to true. After exiting the basic synchronization barrier, if the reduction value is true, the thread repeats exchanging the task stolen flag value and entering the basic synchronization barrier. Other embodiments are described and claimed.
摘要翻译：用于多线程同步和工作窃取的技术包括在线程团队中执行两个或多个线程的计算设备。线程执行其任务队列中的所有任务，然后将其关联的任务被盗标志值与false进行交换，并将该值存储在临时标志中。随后，线程进入基本同步屏障。计算设备对线程团队的临时标志执行逻辑或减少以产生减小值。在等待线程团队的其他线程进入障碍时，线程可能从受害者线程中窃取任务，并将受害者线程的任务被盗标志设置为true。退出基本同步屏障后，如果缩减值为真，则线程重复交换任务被盗标志值并进入基本同步屏障。描述和要求保护其他实施例。

2. 发明申请

US20160170812A1 TECHNOLOGIES FOR EFFICIENT SYNCHRONIZATION BARRIERS WITH WORK STEALING SUPPORT 有权
标题翻译：高效同步障碍技术与工作保障支持技术
公开(公告)号：US20160170812A1
公开(公告)日：2016-06-16
申请号：US14568831
申请日：2014-12-12
申请人： Arch D. Robison , Alejandro Duran Gonzalez
发明人： Arch D. Robison , Alejandro Duran Gonzalez
IPC分类号： G06F9/52 , G06F9/46
CPC分类号： G06F9/522 , G06F9/4856
摘要： Technologies for multithreaded synchronization and work stealing include a computing device executing two or more threads in a thread team. A thread executes all of the tasks in its task queue and then exchanges its associated task stolen flag value with false and stores that value in a temporary flag. Subsequently, the thread enters a basic synchronization barrier. The computing device performs a logical-OR reduction over the temporary flags of the thread team to produce a reduction value. While waiting for other threads of the thread team to enter the barrier, the thread may steal a task from a victim thread and set the task stolen flag of the victim thread to true. After exiting the basic synchronization barrier, if the reduction value is true, the thread repeats exchanging the task stolen flag value and entering the basic synchronization barrier. Other embodiments are described and claimed.
摘要翻译：用于多线程同步和工作窃取的技术包括在线程团队中执行两个或多个线程的计算设备。线程执行其任务队列中的所有任务，然后将其关联的任务被盗标志值与false进行交换，并将该值存储在临时标志中。随后，线程进入基本同步屏障。计算设备对线程团队的临时标志执行逻辑或减少以产生减小值。在等待线程团队的其他线程进入障碍时，线程可能从受害者线程中窃取任务，并将受害者线程的任务被盗标志设置为true。退出基本同步屏障后，如果缩减值为真，则线程重复交换任务被盗标志值并进入基本同步屏障。描述和要求保护其他实施例。

3. 发明授权

US06370685B1 Data-flow method of analyzing definitions and uses of L values in programs 有权
标题翻译：分析程序中L值的定义和使用的数据流方法
公开(公告)号：US06370685B1
公开(公告)日：2002-04-09
申请号：US09226804
申请日：1999-01-06
申请人： Arch D. Robison
发明人： Arch D. Robison
IPC分类号： G06F945
CPC分类号： G06F8/433
摘要： A method for analyzing and optimizing programs that contain pointers or aggregates or both, such as found in the languages C, C++, FORTRAN-90, Ada, and Java is disclosed. The program is represented as a control flow graph. The method applies to storage locations (lvalues) computed by instructions in a program. The data flow analysis distinguishes when a definition might reach a use, and if so, whether the expression defining the address of the defined lvalue may have changed. The method ignores changes to the addressing expression where a definition does not reach. The lattice values and functions employed by the analysis are compactly represented as packed bit vectors, and operated upon in a parallel bitwise fashion. Despite the generality of definitions that define lvalues specified by expressions, the present invention computes the reachability of the definitions with a single data-flow framework that requires only one fixed-point solution per data-flow problem.
摘要翻译：公开了一种用于分析和优化包含指针或聚合或两者的程序的方法，例如在C，C ++，FORTRAN-90，Ada和Java语言中找到的方法。该程序表示为控制流程图。该方法适用于由程序中的指令计算的存储位置（l值）。数据流分析可以区分定义何时达成使用，如果是，则定义定义的左值的地址的表达式是否可能已更改。该方法忽略对定义不到达的寻址表达式的更改。分析中使用的晶格值和函数被紧密地表示为打包位向量，并且以并行的方式操作。尽管定义了由表达式指定的左值的定义的一般性，但是本发明使用仅需要每个数据流问题的一个定点解决方案的单个数据流框架来计算定义的可达性。

4. 发明授权

US08707324B2 Fair scalable reader-writer mutual exclusion 有权
标题翻译：公平可扩展的读写器互斥
公开(公告)号：US08707324B2
公开(公告)日：2014-04-22
申请号：US13405772
申请日：2012-02-27
申请人： Alexey Kukanov , Arch D. Robison
发明人： Alexey Kukanov , Arch D. Robison
IPC分类号： G06F9/46 , G06F7/00
CPC分类号： G06F9/526
摘要： Implementing fair scalable reader writer mutual exclusion for access to a critical section by a plurality of processing threads is accomplished by creating a first queue node for a first thread, the first queue node representing a request by the first thread to access the critical section; setting at least one pointer within a queue to point to the first queue node, the queue representing at least one thread desiring access to the critical section; waiting until a condition is met, the condition comprising the first queue node having no preceding write requests as indicated by at least one predecessor queue node on the queue; permitting the first thread to enter the critical section in response to the condition being met; and causing the first thread to release a spin lock, the spin lock acquired by a second thread of the plurality of processing threads.
摘要翻译：通过为第一线程创建第一队列节点来实现用于通过多个处理线程访问关键部分的公平可扩展读取器写入器互斥，第一队列节点表示第一线程访问关键部分的请求; 将队列中的至少一个指针设置为指向第一队列节点，所述队列表示希望访问关键部分的至少一个线程; 等待直到满足条件，所述条件包括由队列上的至少一个前导队列节点指示的没有先前写入请求的第一队列节点; 允许第一线程响应于满足的条件进入临界区; 并且使所述第一螺纹释放旋转锁定，所述自旋锁由所述多个处理线程中的第二线程获取。

5. 发明授权

US07165245B2 Pruning local graphs in an inter-procedural analysis solver 失效
标题翻译：在程序间分析求解器中修剪本地图
公开(公告)号：US07165245B2
公开(公告)日：2007-01-16
申请号：US09844345
申请日：2001-04-27
申请人： Arch D. Robison
发明人： Arch D. Robison
IPC分类号： G06F9/45
CPC分类号： G06F8/43
摘要： The present invention is a method and system to reduce storage in a inter-procedural analysis solver. In one embodiment, local graphs are pruned. The local graphs represent local problems, which correspond to separately compilable components in a software program. Each of the local graphs has edges and vertices. Each edge has a transfer function. Each vertex has a value. Values of the local graph form a lattice under a partial ordering.
摘要翻译：本发明是减少在程序间分析求解器中存储的方法和系统。在一个实施例中，修剪局部图。本地图表示本地问题，它们对应于软件程序中可单独编译的组件。每个局部图都有边和顶点。每个边缘都有传递函数。每个顶点都有一个值。局部图形的值在部分排序下形成一个格子。

6. 发明申请

US20160170813A1 TECHNOLOGIES FOR FAST SYNCHRONIZATION BARRIERS FOR MANY-CORE PROCESSING 有权
标题翻译：用于多核处理的快速同步障碍的技术
公开(公告)号：US20160170813A1
公开(公告)日：2016-06-16
申请号：US14568890
申请日：2014-12-12
申请人： Arch D. Robison
发明人： Arch D. Robison
IPC分类号： G06F9/52
CPC分类号： G06F9/522
摘要： Technologies for multithreaded synchronization including a computing device having a many-core processor. Each processor core includes multiple hardware threads. A hardware thread executed by a processor core enters a synchronization barrier and synchronizes with other hardware threads executed by the same processor core. After synchronization, the hardware thread synchronizes with a source hardware thread that may be executed by a different processor core. The source hardware thread may be assigned using an n-way shuffle of all hardware threads, where n is the number of hardware threads per processor core. The hardware thread resynchronizes with the other hardware threads executed by the same processor core. The hardware thread alternately synchronizes with the source hardware thread and the other hardware threads executed by the same processor core until all hardware threads have synchronized. The computing device may reduce a Boolean value over the synchronization barrier. Other embodiments are described and claimed.
摘要翻译：包括具有多核处理器的计算设备的多线程同步技术。每个处理器核心包括多个硬件线程。由处理器核心执行的硬件线程进入同步屏障，并与同一处理器核心执行的其他硬件线程同步。同步后，硬件线程与可能由不同处理器核心执行的源硬件线程同步。源硬件线程可以使用所有硬件线程的n次shuffle进行分配，其中n是每个处理器核心的硬件线程数。硬件线程与同一处理器核心执行的其他硬件线程重新同步。硬件线程与源硬件线程和由相同处理器核心执行的其他硬件线程交替同步，直到所有硬件线程都已同步。计算设备可以减少超过同步屏障的布尔值。描述和要求保护其他实施例。

7. 发明授权

US08108867B2 Preserving hardware thread cache affinity via procrastination 有权
标题翻译：通过拖延保护硬件线程缓存亲和力
公开(公告)号：US08108867B2
公开(公告)日：2012-01-31
申请号：US12215154
申请日：2008-06-24
申请人： Arch D. Robison
发明人： Arch D. Robison
IPC分类号： G06F9/30
CPC分类号： G06F9/5033 , G06F9/52
摘要： A method, device, system, and computer readable medium are disclosed. In one embodiment the method includes managing one or more threads attempting to steal task work from one or more other threads. The method will block a thread from stealing a mailed task that is also residing in another thread's task pool. The blocking occurs when the mailed task was mailed to an idle third thread. Additionally, some tasks are deferred instead of immediately spawned.
摘要翻译：公开了一种方法，装置，系统和计算机可读介质。在一个实施例中，该方法包括管理尝试从一个或多个其他线程窃取任务工作的一个或多个线程。该方法将阻止线程窃取也驻留在另一个线程的任务池中的邮件任务。当邮寄的任务邮寄到空闲的第三个线程时，会发生阻止。另外，一些任务被推迟，而不是立即产生。

8. 发明申请

US20090248776A1 ADVANCE TRIP COUNT COMPUTATION IN A CONCURRENT PROCESSING ENVIRONMENT 有权
标题翻译：同步处理环境中的提前计数计算
公开(公告)号：US20090248776A1
公开(公告)日：2009-10-01
申请号：US12057287
申请日：2008-03-27
申请人： Arch D. Robison
发明人： Arch D. Robison
IPC分类号： G06F7/72
CPC分类号： G06F8/4441
摘要： A method for computing a trip count for a loop in advance of the execution of the loop is provided. The method comprises identifying the elements of a loop; returning infinity, if a first index value satisfies a first condition and that a first step size is equal to zero; modifying the first index value and the first step size, if the first index value satisfies the first condition, when the first step size is not equal to zero, and the first step size is greater than half of a first modulus; returning the result computed by applying a formula that divides the difference between a first condition value and the first index value by the first step size and rounds up to a next integer when there is a non-zero remainder; and returning a second trip count for a second loop based on the elements of the first loop.
摘要翻译：提供了一种用于在执行循环之前计算循环的跳闸计数的方法。该方法包括识别循环的元素; 如果第一索引值满足第一条件并且第一步长等于零则返回无穷大; 如果第一指标值满足第一条件，第一步长不等于零，第一步长大于第一模数的一半，则修改第一索引值和第一步长; 通过应用将第一条件值和第一索引值之间的差分除以第一步长的公式返回所计算的结果，并且当存在非零余数时向上舍入到下一个整数; 并且基于第一循环的元素返回第二循环的第二行程计数。

9. 发明授权

US5790866A Method of analyzing definitions and uses in programs with pointers and aggregates in an optimizing compiler 失效
标题翻译：在优化编译器中分析指针和聚合的程序中的定义和用法的分析方法
公开(公告)号：US5790866A
公开(公告)日：1998-08-04
申请号：US388271
申请日：1995-02-13
申请人： Arch D. Robison
发明人： Arch D. Robison
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/433 , G06F8/434 , G06F8/4435
摘要： A method for analyzing and optimizing programs that contain pointers and/or aggregates, such as found in the languages C, C++, FORTRAN-90, and Ada. The method applies to storage locations (lvalues) and values (rvalues) computed by expressions. Data-flow analysis is performed on two levels. The bottom level determines when an rvalue computed at one point in a program is the same if recomputed at a later point in the program. The top level computes reaching definitions, based upon information provided by the bottom level. Each destination lvalue may be designated by an arbitrary rvalue (pointer-expression). Splitting of data-flow analysis into two levels allows computation of reaching definitions that involve assignments to lvalues with designating rvalues that are arbitrary expressions. Furthermore, for aggregate lvalues, which themselves may contain components that are pointers to other aggregates, data-flow analysis is done on a component-by-component basis. Data-flow analysis is then used to forward-substitute definitions and remove "dead" assignments.
摘要翻译：一种用于分析和优化包含指针和/或聚合的程序的方法，例如以C，C ++，FORTRAN-90和Ada语言。该方法适用于由表达式计算的存储位置（lvalues）和值（rvalue）。数据流分析在两个层次上进行。底层决定了在程序中的某一点计算出的r值在程序中的稍后重新计算时是否相同。顶层根据底层提供的信息计算达成的定义。每个目标左值可以由任意的rvalue（指针表达式）指定。将数据流分析分为两个层次，可以计算涉及到左值赋值的定义，并指定任意表达式的值。此外，对于本身可能包含指向其他聚合的指针的聚合值，数据流分析是在逐个组件的基础上进行的。然后使用数据流分析来转发替换定义并删除“死”分配。

10. 发明申请

US20150012729A1 Method and system of compiling program code into predicated instructions for excution on a processor without a program counter 有权
标题翻译：将程序代码编译成用于在没有程序计数器的处理器上排除的预定指令的方法和系统
公开(公告)号：US20150012729A1
公开(公告)日：2015-01-08
申请号：US13987131
申请日：2013-07-02
申请人： Arch D. Robison
发明人： Arch D. Robison
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F8/41
摘要： A predicated instruction compilation system includes a control flow graph generation module to generate a control flow graph of a program code to be compiled into the predicated instructions to be executed on a processor that does not include any program counter. Each of the instructions includes a predicate guard and a predicate update. The compilation system also includes a control flow transformation module to automatically generate the predicate guard and an update to the predicate state on the processor. A computer-implemented method of compiling a program code into predicated instructions is also described.
摘要翻译：预测指令编译系统包括控制流图生成模块，用于生成将被编译为要在不包括任何程序计数器的处理器上执行的预定指令的程序代码的控制流程图。每个指令都包含谓词保护和谓词更新。编译系统还包括一个控制流转换模块，用于自动生成谓词保护和对处理器上的谓词状态的更新。还描述了将程序代码编译成预定指令的计算机实现的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式