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1. 发明授权

US11640303B2 Calculating device 有权
公开(公告)号：US11640303B2
公开(公告)日：2023-05-02
申请号：US17027744
申请日：2020-09-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kosuke Tatsumura , Hayato Goto
IPC分类号： G06F9/38 , G06F7/72 , G06F9/30 , G06F7/57
摘要： According to one embodiment, a calculating device includes a first memory, a second memory, a third memory, a first arithmetic module, a second arithmetic module, a first conductive line electrically connecting a first output terminal of the first memory and a first input terminal of the first arithmetic module, a second conductive line electrically connecting a second output terminal of the first memory and a first input terminal of the second arithmetic module, a third conductive line electrically connecting a first output terminal of the second memory and a second input terminal of the second arithmetic module, a fourth conductive line electrically connecting a first output terminal of the third memory and a third input terminal of the second arithmetic module, and a fifth conductive line electrically connecting a first output terminal of the second arithmetic module and a second input terminal of the first arithmetic module.

2. 发明授权

US11636373B2 Measurement based uncomputation for quantum circuit optimization 有权
公开(公告)号：US11636373B2
公开(公告)日：2023-04-25
申请号：US17719357
申请日：2022-04-12
申请人： Google LLC
发明人： Craig Gidney
IPC分类号： G06N10/00 , G11C11/4063 , G06F7/48 , G06F7/72 , G06F7/505 , G06F17/10 , H04B10/70
摘要： Methods and apparatus for optimizing a quantum circuit. In one aspect, a method includes identifying one or more sequences of operations in the quantum circuit that un-compute respective qubits on which the quantum circuit operates; generating an adjusted quantum circuit, comprising, for each identified sequence of operations in the quantum circuit, replacing the sequence of operations with an X basis measurement and a classically-controlled phase correction operation, wherein a result of the X basis measurement acts as a control for the classically-controlled correction phase operation; and executing the adjusted quantum circuit.

3. 发明申请

US20230081619A1 METHOD TO QUANTIFY TRANSIENT FORCE AND MOMENT 有权
公开(公告)号：US20230081619A1
公开(公告)日：2023-03-16
申请号：US17477270
申请日：2021-09-16
申请人： Hitachi, Ltd.
发明人： Akira Inoue
IPC分类号： G06F30/20 , G06F17/16 , G06F7/72
摘要： In example implementations described herein, there are systems and methods for computation of force and moment in the time domain for a physical system including one or more sensors, which can involve obtaining material properties and first modal properties of the physical system; generating a material property matrix from the material properties and second modal properties from the obtained modal properties; measuring, via the sensors, a set of motion responses of the physical system; obtaining first quantities based on the second modal properties and the material property matrix; calculating a first intermediate matrix from the second modal properties and the set of motion responses; recursively computing, for each time step during measurement of the response, a second intermediate matrix based on (1) the first quantities, (2) the second modal properties, (3) the first intermediate matrix, and (4) a previously computed second intermediate matrix from at least one previous time step; and calculating the force and the moment for each time step during the measurement of the set of motion responses based on the second intermediate matrix and the second modal properties.

4. 发明授权

US11569980B2 Combined SBox and inverse SBox cryptography 有权
公开(公告)号：US11569980B2
公开(公告)日：2023-01-31
申请号：US16689466
申请日：2019-11-20
申请人： International Business Machines Corporation
发明人： Logesh Subbumurugesan , Archana Ravikumar , Umadevi Sureshbabu
IPC分类号： H04L9/06 , H03M13/09 , G06F7/72 , G06F17/16 , H03M13/15
摘要： Hardware circuitry defines logic for both Sbox generation and inverse Sbox generation via generating a multiplicative inverse matrix as a truth table for data. The hardware circuitry receives input plain text to be encrypted. The hardware circuitry divides the input plain text to be encrypted. The hardware circuitry feeds multiplicative inverse values generated from the input plain text to a transformer module for performing affine to encrypt the plain text data. The hardware circuitry receives encrypted data to be decrypted. The hardware circuitry divides the encrypted data to be decrypted. The hardware circuitry feeds multiplicative inverse generated from the encrypted data to the transformer module for performing inverse affine to decrypt the encrypted data.

5. 发明申请

US20230026331A1 High Performance Systems And Methods For Modular Multiplication 有权
公开(公告)号：US20230026331A1
公开(公告)日：2023-01-26
申请号：US17952085
申请日：2022-09-23
申请人： Intel Corporation
发明人： Sergey Gribok , Bogdan Pasca , Martin Langhammer
IPC分类号： G06F7/72 , G06F7/544 , G06F7/523 , G06F7/50 , G06F1/03
摘要： A circuit system for performing modular reduction of a modular multiplication includes multiplier circuits that receive a first subset of coefficients that are generated by summing partial products of a multiplication operation that is part of the modular multiplication. The multiplier circuits multiply the coefficients in the first subset by constants that equal remainders of divisions to generate products. Adder circuits add a second subset of the coefficients and segments of bits of the products that are aligned with respective ones of the second subset of the coefficients to generate sums.

6. 发明授权

US11551131B2 Hamiltonian simulation based on simultaneous-diagonalization 有权
公开(公告)号：US11551131B2
公开(公告)日：2023-01-10
申请号：US16803076
申请日：2020-02-27
申请人： International Business Machines Corporation
发明人： Ewout van den Berg , Paul Kristan Temme
IPC分类号： G06N10/20 , G06N10/00 , G06F7/72 , G06F17/16 , G06F9/30 , G06F30/20 , G06F111/10
摘要： Systems and techniques that facilitate Hamiltonian simulation based on simultaneous-diagonalization are provided. In various embodiments, a partition component can partition one or more Pauli operators of a Hamiltonian into one or more subsets of commuting Pauli operators. In various embodiments, a diagonalization component can generate one or more simultaneous-diagonalization circuits corresponding to the one or more subsets. In various aspects, a one of the one or more simultaneous-diagonalization circuits can diagonalize the commuting Pauli operators in a corresponding one of the one or more subsets. In various embodiments, an exponentiation component can generate one or more exponentiation circuits corresponding to the one or more subsets. In various aspects, a one of the one or more exponentiation circuits can exponentiate the simultaneously diagonalized commuting Pauli operators in a corresponding one of the one or more subsets. In various embodiments, a simulation component can concatenate the one or more simultaneous-diagonalization circuits, the one or more exponentiation circuits, and one or more adjoints of the one or more simultaneous-diagonalization circuits of the one or more subsets to simulate a time evolution of the Hamiltonian.

7. 发明申请

US20230004359A1 COMPUTER-READABLE RECORDING MEDIUM STORING CONTRACT PROGRAM, CONTRACT METHOD, AND INFORMATION PROCESSING APPARATUS 有权
公开(公告)号：US20230004359A1
公开(公告)日：2023-01-05
申请号：US17704330
申请日：2022-03-25
申请人： FUJITSU LIMITED
发明人： Toshihiro Shimizu , Akihito Nakamura , Akihiro Kuwabara , Motohiro Kosaki
IPC分类号： G06F7/72 , G06F11/10
摘要： A recording medium stores a program causing a computer to execute a process including: setting, for each order having a condition that a contract count is designated, a polynomial having a contract count under the condition; representing an order status in which the orders are combined, with a polynomial on a finite field having a remainder obtained by dividing a coefficient of each term in a polynomial obtained by multiplying the polynomials corresponding to the orders; updating the polynomial on the finite field to a polynomial on a finite field representing an order status after a first order is combined, by multiplying the polynomial by a polynomial corresponding to the first order; and detecting an error in the polynomial after the update when a coefficient which is not 0 of a term in the polynomial before the update is 0 in the polynomial.

8. 发明申请

US20220405977A1 METHODS AND DECOMPRESSION UNITS FOR DECOMPRESSING A COMPRESSED BLOCK OF IMAGE DATA 有权
公开(公告)号：US20220405977A1
公开(公告)日：2022-12-22
申请号：US17890920
申请日：2022-08-18
申请人： Imagination Technologies Limited
发明人： Xile Yang
IPC分类号： G06T9/00 , G06F7/50 , G06F7/72 , G06T3/40
摘要： Methods and decompression units for decompressing data from a compressed block of image data, the compressed block of image data representing a block of image data comprising a plurality of image element values, the image element values being divisible into at least a first value and a second value such that the block of image data comprises a two-dimensional block of first values. The method comprises: analysing a header of the compressed block of image data to identify (i) a location in a body of the compressed block of image data of a fixed-length parameter that corresponds to a first desired value in the two-dimensional block of first values, and (ii) common base information for the first desired value, the common base information being common to a first set of values comprising all of the two-dimensional block of first values or a portion of the two-dimensional block of first values that includes the first desired value; retrieving the fixed-length parameter that corresponds to the first desired value from the identified location in the body of the compressed block of image data; and generating the first desired value from the common base information and the fixed-length parameter.

9. 发明授权

US11508263B2 Low complexity conversion to Montgomery domain 有权
公开(公告)号：US11508263B2
公开(公告)日：2022-11-22
申请号：US16911356
申请日：2020-06-24
申请人： Western Digital Technologies, Inc.
发明人： Ishai Ilani , Noam Weber
IPC分类号： G06F21/00 , G09C1/00 , G06F7/72
摘要： Disclosed herein is an apparatus for calculating a cryptographic component R2 mod n for a cryptographic function, where n is a modulo number and R is a constant greater than n. The apparatus comprises a processor configured to set a start value to be equal to R mod n, perform b iterations of a shift and subtract operation on the start value to produce a base value, wherein the start value is set to be equal to the base value after each iteration, set a multiplication operand to be equal to the base value, and perform k iterations of a Montgomery modular multiplication of the multiplication operand with the multiplication operand to produce an intermediate result, wherein the multiplication operand is set to be equal to the intermediate result after each iteration, wherein the shift and subtract operation comprises determining a shifted start value which is equivalent to the start value multiplied by two, and subtracting n from the shifted start value if the shifted start value is greater than or equal to n.

10. 发明授权

US11496370B1 System and methods for multipath data communications 有权
公开(公告)号：US11496370B1
公开(公告)日：2022-11-08
申请号：US17165345
申请日：2021-02-02
申请人： Jump Algorithms, LLC
发明人： Kevin J. Bowers , Nicholas E. Bridge
IPC分类号： H04L41/14 , G06F7/72 , H03M13/00 , G06N5/00 , H04L9/06 , H04L43/0876 , H04L41/142
摘要： A system for transmitting information may include a server that generates pseudo-random superpositions, each superposition including multiple packet fragments encoded using a Galois field. The system may transmit the superpositions across a plurality of communication links, which form a single logical path, to a client device. Communication links may include a combination of diverse communication channels, and more preferably one or more low latency (but low bandwidth) communication links and one or more high bandwidth (but high latency) communication links. Advantageously, the use of a plurality of communication links may facilitate transmitting information quickly and reliably.

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