专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20230005209A1 CIRCUITRY AND METHOD 有权
公开(公告)号：US20230005209A1
公开(公告)日：2023-01-05
申请号：US17363259
申请日：2021-06-30
申请人： Arm Limited
发明人： Harsha VALSARAJU , Javier Diaz Bruguera
IPC分类号： G06T15/06 , G06T1/20 , G06F7/487 , G06F7/499 , G06F9/50
摘要： Circuitry comprises ray tracing circuitry comprising a plurality of floating-point circuitries to perform floating-point processing operations to detect intersection between a virtual ray defined by a ray direction and a test region, the floating-point circuitries operating to a given precision to generate an output floating-point value comprising a significand and an exponent; in which at least some of the plurality of floating-point circuitries are configured to round using a predetermined directed rounding mode any denormal floating-point value generated by operation of that circuitry so as to output normal values, a denormal floating-point value being a floating-point value in which the significand comprises one or more leading zeroes.

2. 发明授权

US11281428B2 Conversion circuitry 有权
公开(公告)号：US11281428B2
公开(公告)日：2022-03-22
申请号：US16299322
申请日：2019-03-12
申请人： Arm Limited
发明人： Javier Diaz Bruguera
IPC分类号： G06F7/48
摘要： A data processing apparatus is provided to convert a plurality of signed digits to an output value, the data processing apparatus comprising: receiver circuitry to receive, at each of a plurality of iterations, a signed digit from the plurality of signed digits, and previous intermediate data. Conversion circuitry performs a negative-output conversion from the signed digit to an unsigned digit, such that the output value comprising the unsigned digit is negative. Concatenation circuitry concatenate bits of the unsigned digit and bits of the previous intermediate data to produce updated intermediate data and output circuitry provides the updated intermediate data as the previous intermediate data of a next iteration. After the plurality of iterations, the output circuitry outputs at least part of the updated intermediate data as the output value.

3. 发明授权

US10140094B2 Rounding circuitry and method 有权
公开(公告)号：US10140094B2
公开(公告)日：2018-11-27
申请号：US15162804
申请日：2016-05-24
申请人： ARM LIMITED
发明人： Javier Diaz Bruguera
IPC分类号： G06F7/499 , G06F7/50
摘要： A data processing apparatus for performing rounding on an input value to produce a rounded form output value includes floor calculation circuitry that receives the input value in redundant-representation and generates two candidates of a floor of the input value in non-redundant representation. Ceiling calculation circuitry receives the input value in redundant-representation and generates two candidates of a ceiling of the input value in non-redundant representation. Selection circuitry outputs one of the two candidates of the floor of said input value and the two candidates of the ceiling of said input value as the rounded form output value, based on a sign of a residual value associated with the input value. Each of the two candidates of the floor of the input value correspond with different values of the sign of the residual value and each of the two candidates of the ceiling of said input value correspond with different values of the sign of said residual value.

4. 发明授权

US11119731B2 Apparatus and method for rounding 有权
公开(公告)号：US11119731B2
公开(公告)日：2021-09-14
申请号：US16550565
申请日：2019-08-26
申请人： Arm Limited
发明人： Javier Diaz Bruguera
IPC分类号： G06F7/499 , G06F7/48
摘要： A data processing apparatus is provided to convert a plurality of signed digits to an output value. Receiver circuitry receives, at each of a plurality of iterations, one of the plurality of signed digits, each of the signed digits comprising a number of bits dependent on a radix. The signed digits being used to form an unrounded output value followed by zero or more extra bits. Adjustment circuitry adjusts a least-significant digit of the unrounded output value to produce an incremented unrounded output value after the plurality of iterations. Rounding circuitry selects from among the unrounded output value and the incremented unrounded output value to produce the output value. The adjustment circuitry is adapted, when a value of a position of a least-significant bit of the unrounded output value is greater than or equal to the radix divided by two, to adjust a subset of the digits of the unrounded output value.

5. 发明授权

US10216481B2 Digit recurrence division with scaling and digit selection using intermediate value 有权
公开(公告)号：US10216481B2
公开(公告)日：2019-02-26
申请号：US15409749
申请日：2017-01-19
申请人： ARM Limited
发明人： Javier Diaz Bruguera
IPC分类号： G06F7/491 , G06F7/535
摘要： A data processing apparatus is provided to perform a digit-recurrence division operation to determine a quotient as a result of dividing a dividend by a divisor. Scaling circuitry scales the dividend and the divisor by a factor to produce a scaled dividend and a scaled divisor. Digit recurrence circuitry performs one or more iterations of the digit-recurrence division operation on the scaled dividend and the scaled divisor, with each iteration producing a digit of the quotient and a remainder value. The remainder value is provided as an input to the digit recurrence circuitry for a subsequent iteration. Initialization circuitry performs a first iteration of the one or more iterations and provides the digit of the quotient after the first iteration. The initialization circuitry receives, as an input, an intermediate value produced by the scaling circuitry while scaling the dividend.

6. 发明申请

US20210255831A1 METHOD, SYSTEM AND DEVICE FOR MULTI-CYCLE DIVISION OPERATION 有权
公开(公告)号：US20210255831A1
公开(公告)日：2021-08-19
申请号：US16791272
申请日：2020-02-14
申请人： Arm Limited
发明人： Javier Diaz Bruguera
IPC分类号： G06F7/535 , G06F7/72 , G06F7/57 , G06F9/30
摘要： The present disclosure relates generally to arithmetic units of processors, and may relate more particularly to multi-cycle division operations.

7. 发明授权

US10353671B2 Circuitry and method for performing division 有权
公开(公告)号：US10353671B2
公开(公告)日：2019-07-16
申请号：US14994601
申请日：2016-01-13
申请人： ARM LIMITED
发明人： Javier Diaz Bruguera
IPC分类号： G06F7/537 , G06F7/487
摘要： A data processing apparatus comprises signal receiving circuitry to receive a signal corresponding to a divide instruction that identifies a dividend x and a divisor d. Processing circuitry performs, in response to said divide instruction, a radix-N division algorithm to generate a result value q=x/d, where N is an integer power of 2 and greater than 1. Said division algorithm comprises a plurality of iterations, each of said plurality of iterations being performed by quotient digit calculation circuitry to determine a quotient value of that iteration q[i+1] based on a remainder value of a previous iteration rem[i]; and remainder calculation circuitry to determine a remainder value of that iteration rem[i+1] based on said quotient value of that iteration q[i+1] and said remainder value of said previous iteration rem[i]. Result calculation circuitry derives said result value q based on each quotient value selected by said digit selection circuitry for each of said plurality of iterations. For at least some of said plurality of iterations, said quotient digit calculation circuitry speculatively determines a set of candidate values before a quotient value of said previous iteration is known and, in response to said quotient value of said previous iteration becoming known, determines said quotient value of that iteration q[i+1] based on one of said candidate values.

8. 发明授权

US11500612B2 Method, system and device for multi-cycle division operation 有权
公开(公告)号：US11500612B2
公开(公告)日：2022-11-15
申请号：US16791272
申请日：2020-02-14
申请人： Arm Limited
发明人： Javier Diaz Bruguera
IPC分类号： G06F7/535 , G06F9/30 , G06F7/57 , G06F7/72
摘要： The present disclosure relates generally to arithmetic units of processors, and may relate more particularly to multi-cycle division operations. Multiple-cycles of a radix-m division operation may be performed to generate one or more signal states representative of a result value based at least in part on a dividend value and a divisor value.

9. 发明授权

US10809980B2 Square root digit recurrence 有权
公开(公告)号：US10809980B2
公开(公告)日：2020-10-20
申请号：US15622429
申请日：2017-06-14
申请人： ARM LIMITED
发明人： Javier Diaz Bruguera , David M. Russinoff
IPC分类号： G06F7/552
摘要： A data processing apparatus is provided, for performing a digit-recurrence square root operation on an input value. Receiver circuitry receives a remainder value of a previous iteration of the digit-recurrence square root operation. Comparison circuitry compares most significant bits of the remainder value of the previous iteration with a number of selection constants, in order to output a next digit of a result of the digit-recurrence square root operation. The comparison circuitry compares at most 3 fractional bits of the remainder value of the previous iteration with the plurality of selection constants.

10. 发明授权

US10409592B2 Multiply-and-accumulate-products instructions 有权
公开(公告)号：US10409592B2
公开(公告)日：2019-09-10
申请号：US15494946
申请日：2017-04-24
申请人： ARM LIMITED
发明人： Neil Burgess , David Raymond Lutz , Javier Diaz Bruguera
IPC分类号： G06F9/30 , G06F7/00
摘要： An apparatus has processing circuitry comprising an L×M multiplier array. An instruction decoder associated with the processing circuitry supports a multiply-and-accumulate-product (MAP) instruction for generating at least one result element corresponding to a sum of respective E×F products of E-bit and F-bit portions of J-bit and K-bit operands respectively, where 1

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式