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    • 5. 发明申请
    • SUPER-JUNCTION SCHOTTKY PIN DIODE
    • 超级立体肖特基二极管
    • US20140239435A1
    • 2014-08-28
    • US14236604
    • 2012-07-19
    • Ning QuAlfred Goerlach
    • Ning QuAlfred Goerlach
    • H01L29/06H01L29/868H01L29/872
    • H01L29/0634H01L29/0649H01L29/66143H01L29/868H01L29/872
    • A semiconductor chip has an n+-doped substrate, above which an n-doped epilayer having trenches is introduced, the trenches being filled with p-doped semiconductor material and in each case having a highly p-doped region at their top side, such that an alternating arrangement of n-doped regions having a first width and p-doped regions having a second width is present. A first metal layer functioning as an anode is provided on the front side of the chip and forms a Schottky contact with the n-doped epilayer and forms an ohmic contact with the highly p-doped regions. A second metal layer which represents an ohmic contact and functioning as a cathode is formed on the rear side of the semiconductor chip. A dielectric layer is provided between each n-doped region and an adjacent p-doped region.
    • 半导体芯片具有n +掺杂的衬底,其上引入具有沟槽的n掺杂外延层,沟槽被p掺杂半导体材料填充,并且在每种情况下在其顶侧具有高p掺杂区域,使得 存在具有第一宽度的n掺杂区域和具有第二宽度的p掺杂区域的交替布置。 用作阳极的第一金属层设置在芯片的正面,并与n掺杂的外延层形成肖特基接触,并与高p掺杂区形成欧姆接触。 表示欧姆接触并用作阴极的第二金属层形成在半导体芯片的后侧。 在每个n掺杂区域和相邻的p掺杂区域之间提供介电层。
    • 6. 发明授权
    • Semiconductor device and method for its production
    • 半导体装置及其制造方法
    • US08334179B2
    • 2012-12-18
    • US12733775
    • 2008-09-17
    • Ning QuAlfred Goerlach
    • Ning QuAlfred Goerlach
    • H01L21/8234
    • H01L29/868H01L29/0611H01L29/0623H01L29/161H01L29/861H01L29/872H01L2924/0002H01L2924/00
    • A semiconductor system is described, which is made up of a highly n-doped silicon substrate and a first n-silicon epitaxial layer, which is directly contiguous to the highly n-doped silicon substrate, and having a p-doped SiGe layer, which is contiguous to a second n-doped silicon epitaxial layer and forms a heterojunction diode, which is situated above the first n-doped silicon epitaxial layer and in which the pn-junction is situated within the p-doped SiGe layer. The first n-silicon epitaxial layer has a higher doping concentration than the second n-silicon epitaxial layer. Situated between the two n-doped epitaxial layers is at least one p-doped emitter trough, which forms a buried emitter, a pn-junction both to the first n-doped silicon epitaxial layer and also to the second n-doped silicon epitaxial layer being formed, and the at least one emitter trough being completely enclosed by the two epitaxial layers.
    • 描述了半导体系统,其由高度n掺杂的硅衬底和与第一n型硅衬底直接相邻并具有p掺杂的SiGe层的第一n型硅外延层组成,其中 与第二n掺杂硅外延层邻接并形成异质结二极管,该异质结二极管位于第一n掺杂硅外延层之上,并且其中pn结位于p掺杂SiGe层内。 第一n硅外延层具有比第二n硅外延层更高的掺杂浓度。 位于两个n掺杂外延层之间的是至少一个p掺杂的发射极沟槽,其形成掩埋发射极,pn结与第一n掺杂硅外延层以及第二n掺杂硅外延层 并且所述至少一个发射极槽被两个外延层完全包围。
    • 7. 发明申请
    • PROTECTIVE ELEMENT FOR ELECTRONIC CIRCUITS
    • 电子电路保护元件
    • US20120280353A1
    • 2012-11-08
    • US13505534
    • 2010-09-21
    • Ning QuAlfred Goerlach
    • Ning QuAlfred Goerlach
    • H01L29/47H01L21/20
    • H01L27/0248H01L29/866H01L29/872H01L29/8725
    • A protective element for electronics has at least one Schottky diode and at least one Zener diode which are located between a power supply and the electronics, the anode of the Schottky diode being connected to the power supply and the cathode of the Schottky diode being connected to the electronics, and the cathode and the anode of the Zener diode are connected to ground. The Schottky diode is a trench MOS barrier junction diode or trench MOS barrier Schottky (TMBS) diode or a trench junction barrier Schottky (TJBS) diode and includes an integrated semiconductor arrangement, which has at least one trench MOS barrier Schottky diode and a p-doped substrate, which is used as the anode of the Zener diode.
    • 用于电子器件的保护元件具有至少一个肖特基二极管和位于电源和电子器件之间的至少一个齐纳二极管,肖特基二极管的阳极连接到电源,肖特基二极管的阴极连接到 电子器件,齐纳二极管的阴极和阳极连接到地。 肖特基二极管是沟槽MOS势垒结二极管或沟槽MOS势垒肖特基(TMBS)二极管或沟槽结势垒肖特基(TJBS)二极管,并且包括集成半导体布置,其具有至少一个沟槽MOS势垒肖特基二极管和p- 掺杂衬底,用作齐纳二极管的阳极。