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1. 发明授权

US09337309B1 Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels 有权
公开(公告)号：US09337309B1
公开(公告)日：2016-05-10
申请号：US14802722
申请日：2015-07-17
申请人： International Business Machines Corporation
发明人： Anirban Basu , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L29/88 , H01L21/329 , H01L29/74 , H01L29/788 , H01L21/336 , H01L29/66 , H01L29/417 , H01L29/10 , H01L29/16 , H01L29/20
CPC分类号： H01L29/66666 , H01L29/0603 , H01L29/1037 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/205 , H01L29/41741 , H01L29/41775 , H01L29/42392 , H01L29/66522 , H01L29/66553 , H01L29/6656 , H01L29/7827 , H01L29/78609 , H01L29/78642 , H01L29/78681 , H01L29/78696
摘要： An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.

2. 发明授权

US09246031B1 Supressing optical loss in nanostructured metals by increasing self-inductance and electron path length 有权
标题翻译：通过增加自感和电子路径长度来抑制纳米结构金属的光损耗
公开(公告)号：US09246031B1
公开(公告)日：2016-01-26
申请号：US14471124
申请日：2014-08-28
申请人： Sang Eon Han , Samuel Clark
发明人： Sang Eon Han , Samuel Clark
IPC分类号： H01L31/0224 , H01L31/0735 , H01L31/073 , H01L21/329
CPC分类号： H01L31/022466 , H01L31/022433 , H01L31/035281 , H01L31/0693 , H01L31/073 , H01L31/0735 , Y02E10/544
摘要： An optoelectronic device configured to operate at an electromagnetic radiation frequency having metal wire electrodes that are optically transparent as a result of the wires having an effective plasma frequency that is equal to or lower than the electromagnetic frequency at which the device operates. The effective plasma frequency of the wire is lowered by configuring the path of the wire between the terminal ends to be meandering, serpentine, U-shaped and in other non-linear configurations.
摘要翻译：一种光电子器件，被配置为以具有等于或低于器件工作的电磁频率的有效等离子体频率的结果，以具有金属线电极的光学透明的电磁辐射频率工作。线的有效等离子体频率通过将终端之间的线的路径配置为曲折，蛇形，U形和其它非线性配置来降低。

3. 发明授权

US08987025B2 Method for manufacturing light emitting diode 有权
标题翻译：制造发光二极管的方法
公开(公告)号：US08987025B2
公开(公告)日：2015-03-24
申请号：US14071668
申请日：2013-11-05
申请人： Advanced Optoelectronic Technology, Inc.
发明人： Chia-Hung Huang , Shih-Cheng Huang , Po-Min Tu , Ya-Wen Lin , Shun-Kuei Yang
IPC分类号： H01L21/205 , H01L21/302 , H01L21/329 , H01L33/58 , H01L33/10 , H01L33/22 , H01L33/32
CPC分类号： H01L33/58 , H01L33/10 , H01L33/22 , H01L33/32
摘要： A manufacturing method for an LED (light emitting diode) includes following steps: providing a substrate; disposing a transitional layer on the substrate, the transitional layer comprising a planar area with a flat top surface and a patterned area with a rugged top surface; coating an aluminum layer on the transitional layer; using a nitriding process on the aluminum layer to form an AlN material on the transitional layer; disposing an epitaxial layer on the transitional layer and covering the AlN material, the epitaxial layer contacting the planar area and the patterned area of the transitional layer, a plurality of gaps being defined between the epitaxial layer and the slugs of the second part of the AlN material in the patterned area of the transitional layer.
摘要翻译： LED（发光二极管）的制造方法包括以下步骤：提供基板; 在衬底上设置过渡层，过渡层包括具有平坦顶表面的平面区域和具有粗糙顶表面的图案区域; 在过渡层上涂覆铝层; 在铝层上使用渗氮工艺在过渡层上形成AlN材料; 在所述过渡层上设置外延层并覆盖所述AlN材料，所述外延层接触所述平坦区域和所述过渡层的图案化区域，所述外延层和所述AlN的第二部分的所述部分之间限定多个间隙过渡层图案区域中的材料。

4. 发明申请

US20140043096A1 POLYSILICON DIODE BANDGAP REFERENCE 有权
标题翻译：多晶硅二极管贴装参考
公开(公告)号：US20140043096A1
公开(公告)日：2014-02-13
申请号：US13570446
申请日：2012-08-09
申请人： Adrian FINNEY
发明人： Adrian FINNEY
IPC分类号： G05F3/02 , H01L21/329 , H01L21/8249 , H01L29/861
CPC分类号： H01L27/0814 , H01L29/8611
摘要： Representative implementations of devices and techniques provide a bandgap reference voltage using at least one polysilicon diode and no silicon diodes. The polysilicon diode is comprised of three portions, a lightly doped portion flanked by a more heavily doped portion on each end.
摘要翻译：器件和技术的代表性实现使用至少一个多晶硅二极管和无硅二极管提供带隙参考电压。多晶硅二极管由三个部分组成，一个轻掺杂部分，其侧面是两端的掺杂部分。

5. 发明申请

US20130334648A1 Methods and Apparatus for High Voltage Diodes 审中-公开
标题翻译：高压二极管的方法和装置
公开(公告)号：US20130334648A1
公开(公告)日：2013-12-19
申请号：US13524902
申请日：2012-06-15
申请人： Wan-Yen Lin , Yi-Feng Chang , Jam-Wem Lee
发明人： Wan-Yen Lin , Yi-Feng Chang , Jam-Wem Lee
IPC分类号： H01L29/861 , H01L21/329
CPC分类号： H01L29/66128 , H01L29/66136 , H01L29/8611
摘要： High voltage diodes are disclosed. A semiconductor device is provided having a P well region; an N well region adjacent to the P well region and forming a p-n junction with the P well region; a P+ region forming an anode at the upper surface of the semiconductor substrate in the P well region; an N+ region forming a cathode at the upper surface of the semiconductor substrate in the N well region; and an isolation structure formed over the upper surface of the semiconductor substrate between the anode and the cathode and electrically isolating the anode and cathode including a first dielectric layer overlying a portion of the upper surface of the semiconductor substrate, and a second dielectric layer overlying a portion of the first dielectric layer and a portion of the upper surface of the semiconductor substrate. Methods for forming the devices are disclosed.
摘要翻译：公开了高电压二极管。提供具有P阱区域的半导体器件; 与P阱区相邻并与P阱区形成p-n结的N阱区; 在P阱区域中的半导体衬底的上表面处形成阳极的P +区域; 在N阱区域中的半导体衬底的上表面处形成阴极的N +区域; 以及在阳极和阴极之间形成在半导体衬底的上表面上的隔离结构，并且电绝缘包括覆盖半导体衬底的上表面的一部分的第一电介质层的阳极和阴极以及覆盖在半导体衬底的上表面的第二电介质层第一电介质层的一部分和半导体衬底的上表面的一部分。公开了形成装置的方法。

6. 发明申请

US20130285208A1 FINFET DIODE WITH INCREASED JUNCTION AREA 失效
标题翻译： FINFET二极管与增加的连接区域
公开(公告)号：US20130285208A1
公开(公告)日：2013-10-31
申请号：US13456921
申请日：2012-04-26
申请人： Theodorus Eduardus Standaert , Kangguo Cheng , Balasubramanian S. Haran , Shom Ponoth , Tenko Yamashita
发明人： Theodorus Eduardus Standaert , Kangguo Cheng , Balasubramanian S. Haran , Shom Ponoth , Tenko Yamashita
IPC分类号： H01L29/861 , H01L21/329
CPC分类号： H01L29/861 , H01L21/845 , H01L27/0266 , H01L29/24 , H01L29/267 , H01L29/6609 , H01L29/785
摘要： A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.
摘要翻译：公开了一种FinFET二极管及其制造方法。在一个实施例中，二极管包括半导体衬底，设置在半导体衬底上的绝缘体层，设置在绝缘体层上的第一硅层，形成在第一硅层的二极管部分中的多个鳍片。第一硅层的区域设置成与多个翅片中的每一个相邻。第二硅层设置在形成在第一硅层的二极管部分中的多个翅片上。栅极环设置在第一硅层上。门环布置成闭合形状，并且包围形成在第一硅层的二极管部分中的多个翅片的一部分。

7. 发明授权

US08569819B1 Doped electrodes for DRAM applications 有权
标题翻译：用于DRAM应用的掺杂电极
公开(公告)号：US08569819B1
公开(公告)日：2013-10-29
申请号：US13915050
申请日：2013-06-11
申请人： Intermolecular, Inc. , Elpida Memory, Inc.
发明人： Xiangxin Rui , Hiroyuki Ode
IPC分类号： H01L27/108 , H01L29/94 , H01L21/8242 , H01L21/329
CPC分类号： H01L28/65 , H01L28/40 , H01L28/60
摘要： A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 μΩcm. Advantageously, the electrode layers are conductive molybdenum oxide.
摘要翻译：形成用于MIM DRAM电容器的金属氧化物第一电极层，其中第一和/或第二电极层含有一个或多个掺杂剂，直到总掺杂浓度，其将不会阻止电极层在随后的退火步骤期间结晶。一种或多种掺杂剂具有大于约5.0eV的功函数。一种或多种掺杂剂的电阻率小于约1000μOggacm。有利地，电极层是导电性氧化钼。

8. 发明授权

US08557654B2 Punch-through diode 有权
标题翻译：穿通二极管
公开(公告)号：US08557654B2
公开(公告)日：2013-10-15
申请号：US12966735
申请日：2010-12-13
申请人： Peter Rabkin , Andrei Mihnea
发明人： Peter Rabkin , Andrei Mihnea
IPC分类号： H01L21/329 , H01L21/33 , H01L27/02 , H01L23/60 , H01L23/62
CPC分类号： H01L27/0255 , G11C2213/72 , G11C2213/74 , H01L27/2409 , H01L27/2481 , H01L29/6609 , H01L29/66121 , H01L29/861 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A punch-through diode and method of fabricating the same are disclosed herein. The punch-through diode may be used as a steering element in a memory device having a reversible resistivity-switching element. For example, a memory cell may include a reversible resistivity-switching element in series with a punch-through diode. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. In other words, the ratio of Ion/Ioff is high. Therefore, the punch-through diode is compatible with bipolar switching in cross-point memory arrays having resistive switching elements.
摘要翻译：本文公开了穿通二极管及其制造方法。穿通二极管可以用作具有可逆电阻率开关元件的存储器件中的转向元件。例如，存储单元可以包括与穿通二极管串联的可逆电阻率开关元件。穿通二极管允许交叉点存储器阵列的双极性操作。穿通二极管可具有对称的非线性电流/电压关系。穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。换句话说，Ion / Ioff的比例很高。因此，穿通二极管与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。

9. 发明申请

US20130202005A1 LASER USING LOCALLY STRAINED GERMANIUM ON SILICON FOR OPTO-ELECTRONIC APPLICATIONS 有权
标题翻译：使用局部应变的锗在硅上进行光电应用的激光
公开(公告)号：US20130202005A1
公开(公告)日：2013-08-08
申请号：US13368162
申请日：2012-02-07
申请人： Birendra Dutt
发明人： Birendra Dutt
IPC分类号： H01S5/026 , H01L21/329
CPC分类号： H01L31/109 , H01L29/165 , H01L31/1804 , H01L31/1812 , H01S5/021 , H01S5/0264 , H01S5/0265 , H01S5/1071 , H01S5/1082 , H01S5/2063 , H01S5/2272 , H01S5/3027 , H01S5/3201 , Y02E10/547 , Y02P70/521
摘要： The subject matter disclosed herein relates to formation of silicon germanium devices with tensile strain. Tensile strain applied to a silicon germanium device in fabrication may improve performance of a silicon germanium laser or light detector.
摘要翻译：本文公开的主题涉及形成具有拉伸应变的硅锗器件。在制造中施加到硅锗器件的拉伸应变可以提高硅锗激光器或光检测器的性能。

10. 发明申请

US20130126888A1 Edge Termination by Ion Implantation in GaN 有权
标题翻译：通过离子注入在GaN中的边缘终止
公开(公告)号：US20130126888A1
公开(公告)日：2013-05-23
申请号：US13301165
申请日：2011-11-21
申请人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , David Bour , Richard J. Brown , Thomas R. Prunty
发明人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , David Bour , Richard J. Brown , Thomas R. Prunty
IPC分类号： H01L29/20 , H01L21/329
CPC分类号： H01L21/2654 , H01L29/0619 , H01L29/0642 , H01L29/2003 , H01L29/66143 , H01L29/6631 , H01L29/66446 , H01L29/66856 , H01L29/8083 , H01L29/868 , H01L29/872
摘要： An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.
摘要翻译：描述了边缘端接的半导体器件，其包括GaN衬底; 在包括离子注入绝缘区域的GaN衬底上生长的掺杂GaN外延层，其中所述离子注入区域具有至少为最大电阻率的90％的电阻率和诸如肖特金属层的导电层设置在所述GaN外延层，其中所述导电层与所述离子注入区域的一部分重叠。使用肖特基接触结构制备肖特基二极管。

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