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    • 5. 发明申请
    • Array Substrate, Its Manufacturing Method, and Display Device
    • 阵列基板,其制造方法和显示装置
    • US20150311222A1
    • 2015-10-29
    • US14310826
    • 2014-06-20
    • BOE TECHNOLOGY GROUP CO., LTD.BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    • Jinchao BaiYao LiuLiangliang LiXiangqian DingZongjie Guo
    • H01L27/12
    • H01L27/124H01L23/5226H01L2924/0002H01L2924/00
    • The present invention provides an array substrate, its manufacturing method, and a display device. The array substrate comprises a gate metal layer, a gate insulating layer, a source/drain metal layer, first common electrode lines arranged on an identical layer to the gate metal layer, a first via hole arranged in the gate insulating layer and corresponding to the first common electrode line, a source/drain metal filling part arranged within the first via hole, a second via hole in communication with the first via hole, and a transparent connection part. The first common electrode lines are, by means of the transparent connection part and the source/drain metal filling part, in electrical connection with each other through the second via hole. According to the present invention, it is able to reduce the depth of the via holes in the array substrate, and improve the uneven diffusion of an alignment layer.
    • 本发明提供阵列基板,其制造方法和显示装置。 阵列基板包括栅极金属层,栅极绝缘层,源极/漏极金属层,布置在与栅极金属层相同的层上的第一公共电极线,布置在栅极绝缘层中并对应于栅极金属层的第一通孔 第一公共电极线,设置在第一通孔内的源极/漏极金属填充部,与第一通孔连通的第二通孔和透明连接部。 第一公共电极线通过透明连接部分和源极/漏极金属填充部分通过第二通孔彼此电连接。 根据本发明,能够减小阵列基板中的通孔的深度,并且可以改善取向层的不均匀扩散。
    • 8. 发明授权
    • Manufacturing method of an array substrate
    • 阵列基板的制造方法
    • US09455282B2
    • 2016-09-27
    • US14519480
    • 2014-10-21
    • BOE TECHNOLOGY GROUP CO., LTD.BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    • Huibin GuoShoukun WangXiaowei LiuYuchun FengZongjie Guo
    • H01L33/00G02F1/1362H01L27/12H01L29/45H01L29/49
    • H01L27/1262H01L27/1288H01L29/458H01L29/4908
    • Provided is a manufacturing method of an array substrate with an etching stop layer. The method includes: forming a pattern including a gate, a gate line and a common electrode line on a substrate through a first patterning process; forming a gate insulation layer, an active layer film and an etching stop layer through a second patterning process; wherein, the etching stop layer corresponds to a gap between a source and a drain which are to be formed, and a via hole exposing the common electrode line is formed above the common electrode line; forming at least an active layer, a pattern including source, drain and data line and a protection layer through a third patterning process; wherein, the protection layer exposes a part of the drain; and forming at least a pixel electrode through a fourth patterning process; wherein, the pixel electrode is electrically connected with the drain.
    • 提供了具有蚀刻停止层的阵列基板的制造方法。 该方法包括:通过第一图案化工艺在衬底上形成包括栅极,栅极线和公共电极线的图案; 通过第二图案化工艺形成栅极绝缘层,有源层膜和蚀刻停止层; 其中,所述蚀刻停止层对应于要形成的源极和漏极之间的间隙,并且在所述公共电极线上方形成暴露所述公共电极线的通孔; 通过第三图案化工艺形成至少有源层,包括源极,漏极和数据线的图案和保护层; 其中,所述保护层暴露所述漏极的一部分; 以及通过第四图案化工艺形成至少一个像素电极; 其中,像素电极与漏极电连接。