专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4774201A Tungsten-silicide reoxidation technique using a CVD oxide cap 失效
标题翻译：使用CVD氧化物盖的硅化钨再氧化技术
公开(公告)号：US4774201A
公开(公告)日：1988-09-27
申请号：US142907
申请日：1988-01-07
申请人： Been-Jon Woo , Wei-Jen Lo
发明人： Been-Jon Woo , Wei-Jen Lo
IPC分类号： H01L21/321 , H01L21/336 , H01L29/49 , H01L21/316
CPC分类号： H01L29/6659 , H01L21/321 , H01L21/32105 , H01L29/4933 , Y10S148/118
摘要： A tungsten silicide reoxidation technique for forming a reoxidation layer in a CMOS MOSFET device. After forming an insulated gate member, which has a tungsten silicide layer overlying a polysilicon layer, a CVD oxide layer is deposited on the exposed and crystallized tungsten silicide layer to function as a cap prior to the formation of the reoxidation layer. The CVD oxide layer operates to slow the passage of oxygen atoms to combine with the tungsten atoms of the silicide layer but allows free migration of silicon atoms from the polysilicon layer to the tungsten silicide surface and combine with the oxygen atoms in forming a substantially planarized and uncontaminated reoxidation layer without the requirement of a substantially pure nitrogen ambient.
摘要翻译：一种用于在CMOS MOSFET器件中形成再氧化层的硅化钨再氧化技术。在形成具有覆盖多晶硅层的硅化钨层的绝缘栅极部件之后，在曝光和结晶的硅化钨层之间沉积CVD氧化物层，以在形成再氧化层之前起到帽的作用。 CVD氧化物层操作以减缓氧原子的通过以与硅化物层的钨原子结合，但是允许硅原子从多晶硅层自由迁移到硅化钨表面，并与氧原子结合形成基本平坦化的和未污染的再氧化层，而不需要基本上纯的氮气氛。

2. 发明授权

US5196361A Method of making source junction breakdown for devices with source-side erasing 失效
标题翻译：源端擦除器件源极结击穿的方法
公开(公告)号：US5196361A
公开(公告)日：1993-03-23
申请号：US700512
申请日：1991-05-15
申请人： Tong-Chern Ong , Been-Jon Woo
发明人： Tong-Chern Ong , Been-Jon Woo
IPC分类号： H01L21/336 , H01L27/115 , H01L29/788
CPC分类号： H01L29/66825 , H01L29/7883 , H01L29/7885 , H01L27/115
摘要： A method for making a device and the device itself which utilizes selectively doping part of the channel directly adjacent to the source to improve source-channel junction breakdown voltage is disclosed. This is accomplished through reduced dopant incorporation in the channel directly adjacent to the source during the channel doping steps. The portion of the channel which receives less channel dopant should not be so great that the charging of the floating gate is significantly altered.
摘要翻译：公开了一种制造器件和器件本身的方法，其利用选择性地掺杂与源极相邻的沟道的一部分来改善源极结击穿电压。这通过在沟道掺杂步骤期间通过与源极直接相邻的沟道中的掺杂剂掺杂减少来实现。接收较少通道掺杂剂的通道的部分不应该太大，使得浮动栅极的充电被显着改变。

3. 发明授权

US4784965A Source drain doping technique 失效
标题翻译：源极漏极掺杂技术
公开(公告)号：US4784965A
公开(公告)日：1988-11-15
申请号：US097532
申请日：1987-09-16
申请人： Been-Jon Woo , Mark A. Holler , Ender Hokeler , Sandra S. Lee
发明人： Been-Jon Woo , Mark A. Holler , Ender Hokeler , Sandra S. Lee
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66598 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7836 , Y10S148/053 , Y10S148/082 , Y10S148/106
摘要： A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.
摘要翻译：描述了形成金属氧化物半导体场效应晶体管（MOSFET）的方法，其中源极和漏极区域以基本上垂直于衬底表面的方式通过离子注入以两个步骤设置，使得杂质的浓度随着横向距离而增加远离栅极电极部件抑制热注入，防止沟道效应，增加穿通电压并增加栅极辅助击穿电压。

4. 发明授权

US4757026A Source drain doping technique 失效
标题翻译：源极漏极掺杂技术
公开(公告)号：US4757026A
公开(公告)日：1988-07-12
申请号：US97539
申请日：1987-09-16
申请人： Been-Jon Woo , Mark A. Holler , Ender Hokelek , Sandra S. Lee
发明人： Been-Jon Woo , Mark A. Holler , Ender Hokelek , Sandra S. Lee
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66598 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7836 , Y10S148/082 , Y10S148/106
摘要： A method of forming complementary metal oxide semiconductor field-effect transistors (CMOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effects, to increase punch through voltage and to increase gate-aided breakdown voltage.
摘要翻译：描述了形成互补金属氧化物半导体场效应晶体管（CMOSFET）的方法，其中源极和漏极区域以基本上垂直于衬底表面的方式通过离子注入以两个步骤设置，使得杂质的浓度随着侧向距离栅电极部件的距离，以抑制热注入，防止通道效应，增加穿通电压并增加栅极辅助击穿电压。

5. 发明申请

US20070210030A1 Method of patterning conductive structure 审中-公开
标题翻译：图案导电结构的方法
公开(公告)号：US20070210030A1
公开(公告)日：2007-09-13
申请号：US11373138
申请日：2006-03-13
申请人： Been-Jon Woo
发明人： Been-Jon Woo
IPC分类号： C23F1/00 , C03C25/68 , H01L21/302
CPC分类号： H01L21/32139
摘要： A method of patterning a conductive structure includes providing a semiconductor substrate, forming a conductive layer on the semiconductor substrate, forming a hard mask layer on the conductive layer and forming a photo-resist layer on the hard mask layer. An isotropic etching is applied to remove a partial region of the photo-resistant layer in order to form a patterned photo-resistant layer. Then, the patterned photo-resistant layer is used as a mask to form a patterned hard mask layer by etching the hard mask layer. Next, the patterned hard mask layer is used as another mask to remove the partial region of the conductive layer to form a patterned conductive layer. The patterned photo-resist layer is only used for etching the hard mask layer, therefore it is able to enhance the resolution when using a thinner photo-resistant layer, furthermore to fabricate a patterned conductive layer with a miniaturized dimensional structure.
摘要翻译：图案化导电结构的方法包括提供半导体衬底，在半导体衬底上形成导电层，在导电层上形成硬掩模层，并在硬掩模层上形成光刻胶层。施加各向同性蚀刻以除去抗光层的部分区域以形成图案化的耐光层。然后，通过蚀刻硬掩模层，将图案化的耐光层用作掩模以形成图案化的硬掩模层。接下来，将图案化的硬掩模层用作另一掩模以去除导电层的部分区域以形成图案化的导电层。图案化的光致抗蚀剂层仅用于蚀刻硬掩模层，因此当使用较薄的耐光层时，能够提高分辨率，此外，制造具有小型化尺寸结构的图案化导电层。

6. 发明授权

US5229631A Erase performance improvement via dual floating gate processing 失效
标题翻译：通过双浮栅处理擦除性能提升
公开(公告)号：US5229631A
公开(公告)日：1993-07-20
申请号：US963938
申请日：1992-10-20
申请人： Been-Jon Woo
发明人： Been-Jon Woo
IPC分类号： H01L21/28 , H01L27/115
CPC分类号： H01L21/28273 , H01L27/115
摘要： A process for fabricating floating gates for electrically programmable and electrically erasable memory cells of the flash EPROM or EEPROM type. The floating gates are a three layer structure. The first layer of the floating gate is a thin polysilicon layer of approximately 300-500 .ANG. thickness. The second layer is a silicon dioxide layer of approximately 20-30 .ANG.. The third layer is polysilicon of approximately 1000-1500 .ANG. thickness. The third layer is doped by implantation of phosphorous. This dopant is driven through the oxide layer to dope the first, thin polysilicon layer in a separate diffusion step or in subsequent high temperature processing. The grain size of the first, thin polysilicon layer is small and uniform from gate to gate due to the thinness of this layer and its light doping. This reduces variations in threshold voltage from gate to gate due to variable polysilicon grain size and orientation. This in turn results in improved yield and cycling endurance.
摘要翻译：一种用于制造闪存EPROM或EEPROM类型的电可编程和电可擦除存储单元的浮动栅极的工艺。浮动门是三层结构。浮栅的第一层是大约300-500安格姆厚度的薄多晶硅层。第二层是大约20-30安培的二氧化硅层。第三层是大约1000-1500 ANGSTROM厚度的多晶硅。第三层通过磷的掺杂掺杂。该掺杂剂被驱动通过氧化物层以在单独的扩散步骤或随后的高温处理中掺杂第一薄的多晶硅层。由于该层的薄度和其轻掺杂，第一薄的多晶硅层的晶粒尺寸小且从栅极到栅极均匀。这可以由于可变多晶硅晶粒尺寸和取向而降低栅极到栅极的阈值电压的变化。这反过来又会提高产量和耐力。

7. 发明授权

US07632736B2 Self-aligned contact formation utilizing sacrificial polysilicon 有权
公开(公告)号：US07632736B2
公开(公告)日：2009-12-15
申请号：US12002752
申请日：2007-12-18
申请人： Max Wei , Been-Jon Woo
发明人： Max Wei , Been-Jon Woo
IPC分类号： H01L21/76 , H01L21/265 , H01L21/425 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76897
摘要： In general, in one aspect, a method includes forming a spacer layer over a substrate having patterned stacks formed therein and trenches between the patterned stacks. A sacrificial polysilicon layer is deposited over the substrate to fill the trenches. A patterning layer is deposited over the substrate and patterned to define contact regions over at least a portion of the trenches. The sacrificial polysilicon layer is etched using the patterned patterning layer to form open regions.

8. 发明授权

US5470772A Silicidation method for contactless EPROM related devices 失效
标题翻译：无接触EPROM相关器件的硅化方法
公开(公告)号：US5470772A
公开(公告)日：1995-11-28
申请号：US67269
申请日：1993-05-24
申请人： Been-Jon Woo
发明人： Been-Jon Woo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash contactless EPROM or EEPROM type. The array of memory cells in these devices have elongated, parallel source and drain regions disposed beneath field oxide regions. The word lines are elongated, parallel strips of polysilicon. A series of SiO.sub.2 depositions using TEOS chemistry in a PECVD process, and etches using sputter etch and plasma processes, is performed. After deposition and etchback, the polysilicon word lines remain exposed while all previous exposed substrate regions between source and drain are covered with SiO.sub.2. A metal deposition and silicidation are performed forming a silicide on the exposed silicon word lines thereby lowering the resistance of the word lines. Since the substrate regions between source and drain is covered between SiO.sub.2 prior to metal deposition and silicidation no silicide is formed in these regions. Therefore the word lines are silicidized in a self aligned process with no need for a photolithographic step after SiO.sub.2 deposition.
摘要翻译：一种用于制造闪存非接触式EPROM或EEPROM类型的非接触电可编程和电可擦除存储单元的工艺。这些器件中的存储器单元阵列具有设置在场氧化物区域之下的细长的平行的源极和漏极区域。字线是细长的，平行的多晶硅条。在PECVD工艺中使用TEOS化学的一系列SiO 2沉积和使用溅射蚀刻和等离子体处理的蚀刻进行。在沉积和回蚀之后，多晶硅字线保持暴露，而源极和漏极之间的所有先前暴露的衬底区域被SiO 2覆盖。进行金属沉积和硅化，在暴露的硅字线上形成硅化物，从而降低字线的电阻。由于源极和漏极之间的衬底区域在金属沉积和硅化之前被覆盖在SiO 2之间，所以在这些区域中不形成硅化物。因此，在自对准工艺中，字线被硅化，在SiO 2沉积之后不需要光刻步骤。

9. 发明授权

US4833099A Tungsten-silicide reoxidation process including annealing in pure nitrogen and subsequent oxidation in oxygen 失效
标题翻译：硅化钨再氧化工艺，包括在纯氮中退火，随后在氧气中氧化
公开(公告)号：US4833099A
公开(公告)日：1989-05-23
申请号：US142906
申请日：1988-01-07
申请人： Been-Jon Woo
发明人： Been-Jon Woo
IPC分类号： H01L21/321 , H01L21/336 , H01L21/8238 , H01L29/423
CPC分类号： H01L29/6659 , H01L21/32105 , H01L21/823835 , H01L29/4232 , Y10S148/003 , Y10S148/118 , Y10S148/147
摘要： A tungsten silicide reoxidation technique for forming a reoxidation layer in a CMOS device is disclosed. After forming an insulated gate member, which has a silicon-rich tungsten silicide layer overlying a polysilicon layer, it is first oxidized and the oxide is removed to expose WSi for forming a particular source/drain doped device. Then it is annealed in a substantially pure nitrogen ambient for a given time period. A subsequent growth of the reoxidation layer over the gate member by introducing oxygen results in a substantially planarized surface. The combination between tungsten and oxygen is prevented.
摘要翻译：公开了一种用于在CMOS器件中形成再氧化层的硅化钨再氧化技术。在形成具有覆盖多晶硅层的富含硅的硅化钨层的绝缘栅极部件之后，首先将其氧化并除去氧化物以暴露WSi以形成特定的源极/漏极掺杂器件。然后将其在基本上纯的氮气环境中退火给定的时间段。通过引入氧在栅极部件上的再氧化层的随后生长导致基本平坦化的表面。防止钨和氧之间的组合。

10. 发明授权

US4728617A Method of fabricating a MOSFET with graded source and drain regions 失效
标题翻译：制造具有分级源极和漏极区域的MOSFET的方法
公开(公告)号：US4728617A
公开(公告)日：1988-03-01
申请号：US926733
申请日：1986-11-04
申请人： Been-Jon Woo , Mark A. Holler , Ender Hokelek , Sandra S. Lee
发明人： Been-Jon Woo , Mark A. Holler , Ender Hokelek , Sandra S. Lee
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66598 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7836 , Y10S148/053 , Y10S148/082 , Y10S148/106 , Y10S438/965
摘要： A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.
摘要翻译：描述了形成金属氧化物半导体场效应晶体管（MOSFET）的方法，其中源极和漏极区域以基本上垂直于衬底表面的方式通过离子注入以两个步骤设置，使得杂质的浓度随着横向距离而增加远离栅极电极部件抑制热注入，防止沟道效应，增加穿通电压并增加栅极辅助击穿电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式