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    • 5. 发明申请
    • Method of patterning conductive structure
    • 图案导电结构的方法
    • US20070210030A1
    • 2007-09-13
    • US11373138
    • 2006-03-13
    • Been-Jon Woo
    • Been-Jon Woo
    • C23F1/00C03C25/68H01L21/302
    • H01L21/32139
    • A method of patterning a conductive structure includes providing a semiconductor substrate, forming a conductive layer on the semiconductor substrate, forming a hard mask layer on the conductive layer and forming a photo-resist layer on the hard mask layer. An isotropic etching is applied to remove a partial region of the photo-resistant layer in order to form a patterned photo-resistant layer. Then, the patterned photo-resistant layer is used as a mask to form a patterned hard mask layer by etching the hard mask layer. Next, the patterned hard mask layer is used as another mask to remove the partial region of the conductive layer to form a patterned conductive layer. The patterned photo-resist layer is only used for etching the hard mask layer, therefore it is able to enhance the resolution when using a thinner photo-resistant layer, furthermore to fabricate a patterned conductive layer with a miniaturized dimensional structure.
    • 图案化导电结构的方法包括提供半导体衬底,在半导体衬底上形成导电层,在导电层上形成硬掩模层,并在硬掩模层上形成光刻胶层。 施加各向同性蚀刻以除去抗光层的部分区域以形成图案化的耐光层。 然后,通过蚀刻硬掩模层,将图案化的耐光层用作掩模以形成图案化的硬掩模层。 接下来,将图案化的硬掩模层用作另一掩模以去除导电层的部分区域以形成图案化的导电层。 图案化的光致抗蚀剂层仅用于蚀刻硬掩模层,因此当使用较薄的耐光层时,能够提高分辨率,此外,制造具有小型化尺寸结构的图案化导电层。
    • 6. 发明授权
    • Erase performance improvement via dual floating gate processing
    • 通过双浮栅处理擦除性能提升
    • US5229631A
    • 1993-07-20
    • US963938
    • 1992-10-20
    • Been-Jon Woo
    • Been-Jon Woo
    • H01L21/28H01L27/115
    • H01L21/28273H01L27/115
    • A process for fabricating floating gates for electrically programmable and electrically erasable memory cells of the flash EPROM or EEPROM type. The floating gates are a three layer structure. The first layer of the floating gate is a thin polysilicon layer of approximately 300-500 .ANG. thickness. The second layer is a silicon dioxide layer of approximately 20-30 .ANG.. The third layer is polysilicon of approximately 1000-1500 .ANG. thickness. The third layer is doped by implantation of phosphorous. This dopant is driven through the oxide layer to dope the first, thin polysilicon layer in a separate diffusion step or in subsequent high temperature processing. The grain size of the first, thin polysilicon layer is small and uniform from gate to gate due to the thinness of this layer and its light doping. This reduces variations in threshold voltage from gate to gate due to variable polysilicon grain size and orientation. This in turn results in improved yield and cycling endurance.
    • 一种用于制造闪存EPROM或EEPROM类型的电可编程和电可擦除存储单元的浮动栅极的工艺。 浮动门是三层结构。 浮栅的第一层是大约300-500安格姆厚度的薄多晶硅层。 第二层是大约20-30安培的二氧化硅层。 第三层是大约1000-1500 ANGSTROM厚度的多晶硅。 第三层通过磷的掺杂掺杂。 该掺杂剂被驱动通过氧化物层以在单独的扩散步骤或随后的高温处理中掺杂第一薄的多晶硅层。 由于该层的薄度和其轻掺杂,第一薄的多晶硅层的晶粒尺寸小且从栅极到栅极均匀。 这可以由于可变多晶硅晶粒尺寸和取向而降低栅极到栅极的阈值电压的变化。 这反过来又会提高产量和耐力。
    • 8. 发明授权
    • Silicidation method for contactless EPROM related devices
    • 无接触EPROM相关器件的硅化方法
    • US5470772A
    • 1995-11-28
    • US67269
    • 1993-05-24
    • Been-Jon Woo
    • Been-Jon Woo
    • H01L21/8247
    • H01L27/11521
    • A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash contactless EPROM or EEPROM type. The array of memory cells in these devices have elongated, parallel source and drain regions disposed beneath field oxide regions. The word lines are elongated, parallel strips of polysilicon. A series of SiO.sub.2 depositions using TEOS chemistry in a PECVD process, and etches using sputter etch and plasma processes, is performed. After deposition and etchback, the polysilicon word lines remain exposed while all previous exposed substrate regions between source and drain are covered with SiO.sub.2. A metal deposition and silicidation are performed forming a silicide on the exposed silicon word lines thereby lowering the resistance of the word lines. Since the substrate regions between source and drain is covered between SiO.sub.2 prior to metal deposition and silicidation no silicide is formed in these regions. Therefore the word lines are silicidized in a self aligned process with no need for a photolithographic step after SiO.sub.2 deposition.
    • 一种用于制造闪存非接触式EPROM或EEPROM类型的非接触电可编程和电可擦除存储单元的工艺。 这些器件中的存储器单元阵列具有设置在场氧化物区域之下的细长的平行的源极和漏极区域。 字线是细长的,平行的多晶硅条。 在PECVD工艺中使用TEOS化学的一系列SiO 2沉积和使用溅射蚀刻和等离子体处理的蚀刻进行。 在沉积和回蚀之后,多晶硅字线保持暴露,而源极和漏极之间的所有先前暴露的衬底区域被SiO 2覆盖。 进行金属沉积和硅化,在暴露的硅字线上形成硅化物,从而降低字线的电阻。 由于源极和漏极之间的衬底区域在金属沉积和硅化之前被覆盖在SiO 2之间,所以在这些区域中不形成硅化物。 因此,在自对准工艺中,字线被硅化,在SiO 2沉积之后不需要光刻步骤。