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1. 发明授权

US08225239B2 Methods for defining and utilizing sub-resolution features in linear topology 有权
标题翻译：在线性拓扑中定义和利用子分辨率特征的方法
公开(公告)号：US08225239B2
公开(公告)日：2012-07-17
申请号：US12479674
申请日：2009-06-05
申请人： Brian Reed , Michael C. Smayling , Joseph N. Hong , Stephen Fairbanks , Scott T. Becker
发明人： Brian Reed , Michael C. Smayling , Joseph N. Hong , Stephen Fairbanks , Scott T. Becker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support placement of a sub-resolution shape. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the sub-resolution shape is placed so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space. Also, one or more sub-resolution shapes are placed between and parallel with neighboring regular layout shapes when windows of lithographic reinforcement associated with each of the neighboring regular layout shapes permit. The sub-resolution shapes may be placed according to a virtual grate, or may be placed based on proximity to edges of the neighboring regular layout shapes.
摘要翻译：正常的布局形状根据虚拟炉排放置。确定与正规布局形状相邻的未被占用的布局空间是否被加强并且沿与正常布局形状垂直的方向延伸的尺寸足够大以支持分分辨率形状的放置。在确定未占用的布局空间足够大以支持分分辨率形状的放置时，子分辨率形状被放置为基本上位于未占用的布局空间内的虚拟格栅的虚拟线上。此外，当与相邻的规则布局形状中的每一个相关联的光刻加固件的窗口允许时，一个或多个子分辨率形状被放置在相邻的规则布局形状之间并与其平行。子分辨率形状可以根据虚拟格栅放置，或者可以基于邻近的规则布局形状的边缘的位置放置。

2. 发明申请

US20090300574A1 Methods for Defining and Utilizing Sub-Resolution Features in Linear Topology 有权
标题翻译：定义和利用线性拓扑中的分解特征的方法
公开(公告)号：US20090300574A1
公开(公告)日：2009-12-03
申请号：US12479674
申请日：2009-06-05
申请人： Brian Reed , Michael C. Smayling , Joseph N. Hong , Stephen Fairbanks
发明人： Brian Reed , Michael C. Smayling , Joseph N. Hong , Stephen Fairbanks
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support placement of a sub-resolution shape. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the sub-resolution shape is placed so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space. Also, one or more sub-resolution shapes are placed between and parallel with neighboring regular layout shapes when windows of lithographic reinforcement associated with each of the neighboring regular layout shapes permit. The sub-resolution shapes may be placed according to a virtual grate, or may be placed based on proximity to edges of the neighboring regular layout shapes.
摘要翻译：正常的布局形状根据虚拟炉排放置。确定与正规布局形状相邻的未被占用的布局空间是否被加强并且沿与正常布局形状垂直的方向延伸的尺寸足够大以支持分分辨率形状的放置。在确定未占用的布局空间足够大以支持分分辨率形状的放置时，子分辨率形状被放置为基本上位于未占用的布局空间内的虚拟格栅的虚拟线上。此外，当与相邻的规则布局形状中的每一个相关联的光刻加固件的窗口允许时，一个或多个子分辨率形状被放置在相邻的规则布局形状之间并与其平行。子分辨率形状可以根据虚拟格栅放置，或者可以基于邻近的规则布局形状的边缘的位置放置。

3. 发明授权

US06889290B2 Memory management apparatus and method 失效
标题翻译：内存管理装置和方法
公开(公告)号：US06889290B2
公开(公告)日：2005-05-03
申请号：US09896597
申请日：2001-06-29
申请人： Joseph N. Hong
发明人： Joseph N. Hong
IPC分类号： G06F12/08
CPC分类号： G06F12/0846
摘要： Cache memory systems, microprocessors, and computer systems, as well as methods of operating a cache memory system are described. The cache memory system includes a cache memory controller coupled to a dynamic cache memory and a static cache memory. The cache memory system provides the advantages of using dynamic memory (having a small circuit real estate requirement) for cache read operations, and static memory for cache write operations. Using the static memory for cache write operations allows the cache memory system to function as a write-back cache, instead of an instruction-only, or write-through cache.
摘要翻译：描述了缓存存储器系统，微处理器和计算机系统，以及操作高速缓存存储器系统的方法。高速缓冲存储器系统包括耦合到动态高速缓冲存储器和静态高速缓冲存储器的高速缓冲存储器控制器。高速缓冲存储器系统提供了使用用于高速缓存读取操作的动态存储器（具有小的电路空间要求）和用于高速缓存写入操作的静态存储器的优点。使用静态存储器进行缓存写入操作允许高速缓存存储器系统用作回写高速缓存，而不是仅指令或直写缓存。

4. 发明授权

US06469953B1 Latch circuit 有权
标题翻译：锁存电路
公开(公告)号：US06469953B1
公开(公告)日：2002-10-22
申请号：US09925148
申请日：2001-08-08
申请人： Joseph N. Hong
发明人： Joseph N. Hong
IPC分类号： G11C800
CPC分类号： G11C8/10 , G11C8/06
摘要： A domino-logic latch device may include a domino-logic block formed, e.g., of a transistor and a static inverter, a precharge transistor configured to precharge a sensing node to a precharge logic level, a logic block arranged between the sensing node and an intermediate node, and configured to receive one or more input signals to be evaluated during a predetermined interval, a latching transistor, arranged between the sensing node and the intermediate node and configured to latch an evaluated logic level of the logic block during the predetermined interval, and a discharge transistor, coupled to the intermediate node, configured to conditionally discharge the sensing node to a discharge logic level based on the input signals evaluated by the logic block.
摘要翻译：多米诺骨牌锁存装置可以包括例如由晶体管和静态反相器形成的多米诺骨牌块，配置成将感测节点预充电到预充电逻辑电平的预充电晶体管，布置在感测节点和中间节点，并且被配置为在预定间隔期间接收要评估的一个或多个输入信号，锁存晶体管，布置在所述感测节点和所述中间节点之间并且被配置为在所述预定间隔期间锁存所述逻辑块的评估逻辑电平，以及耦合到中间节点的放电晶体管，被配置为基于由逻辑块评估的输入信号有条件地将感测节点放电到放电逻辑电平。

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