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    • 5. 发明申请
    • Local interconnect for integrated circuit
    • 集成电路的局部互连
    • US20050156196A1
    • 2005-07-21
    • US11058498
    • 2005-02-15
    • Jeffrey HansonDerryl Allman
    • Jeffrey HansonDerryl Allman
    • H01L21/768H01L23/535H01L21/8238H01L31/072
    • H01L23/535H01L21/76895H01L2924/0002H01L2924/00
    • An integrated circuit having a gate region, a source drain region, and an electrically nonconductive spacer separating the gate region and the source drain region. A local interconnect electrically connects the gate region to the source drain region across the electrically nonconductive spacer. The local interconnect is formed of a semiconducting material reacted with a metal. The local interconnect may be formed by implanting a precursor species into the electrically nonconductive spacer. A metal layer is deposited over at least the electrically nonconductive spacer, and the integrated circuit is heated to form an electrically conductive local interconnect from the metal layer and the precursor species implanted in the electrically nonconductive spacer.
    • 一种具有栅极区域,源极漏极区域和分离栅极区域和源极漏极区域的非导电间隔区的集成电路。 局部互连通过非导电间隔物将栅极区域电连接到源极漏极区域。 局部互连由与金属反应的半导体材料形成。 可以通过将前体物质注入到非导电间隔物中来形成局部互连。 金属层沉积在至少不导电的间隔物上,并且集成电路被加热以形成从金属层和植入在非导电间隔物中的前体物质的导电局部互连。
    • 6. 发明授权
    • Method of design based process control optimization
    • 基于设计的过程控制优化方法
    • US07571397B2
    • 2009-08-04
    • US11265040
    • 2005-11-02
    • Jeffrey HansonMark A. Giewont
    • Jeffrey HansonMark A. Giewont
    • G06F17/50
    • G05B13/021
    • The present invention provides a method of design based process control optimization. In an embodiment, the method of design based process control optimization includes creating a circuit layout database including a design rule set. At least one algorithm is employed to query the circuit layout database to calculate at least one process specification limit. The method includes comparing the calculated at least one process specification limit with at least one predefined technology process tool capability to determine if the calculated at least one process specification limit allows for a manufacturable process. If the calculated at least one process specification limit does not allow for the manufacturable process, the limit may be re-optimized.
    • 本发明提供了一种基于设计的过程控制优化方法。 在一个实施例中,基于设计的过程控制优化的方法包括创建包括设计规则集的电路布局数据库。 采用至少一种算法来查询电路布局数据库以计算至少一个过程规范限制。 该方法包括将所计算的至少一个过程规范限制与至少一个预定义的技术过程工具能力进行比较,以确定所计算的至少一个过程规范限制是否允许可制造过程。 如果计算的至少一个过程规范限制不允许可制造过程,则可以重新优化极限。
    • 7. 发明申请
    • Method of design based process control optimization
    • 基于设计的过程控制优化方法
    • US20070099313A1
    • 2007-05-03
    • US11265040
    • 2005-11-02
    • Jeffrey HansonMark Giewont
    • Jeffrey HansonMark Giewont
    • H01L21/66G01R31/26
    • G05B13/021
    • The present invention provides a method of design based process control optimization. In an embodiment, the method of design based process control optimization includes creating a circuit layout database including a design rule set. At least one algorithm is employed to query the circuit layout database to calculate at least one process specification limit. The method includes comparing the calculated at least one process specification limit with at least one predefined technology process tool capability to determine if the calculated at least one process specification limit allows for a manufacturable process. If the calculated at least one process specification limit does not allow for the manufacturable process, the limit may be re-optimized.
    • 本发明提供了一种基于设计的过程控制优化方法。 在一个实施例中,基于设计的过程控制优化的方法包括创建包括设计规则集的电路布局数据库。 采用至少一种算法来查询电路布局数据库以计算至少一个过程规范限制。 该方法包括将所计算的至少一个过程规范限制与至少一个预定义的技术过程工具能力进行比较,以确定所计算的至少一个过程规范限制是否允许可制造过程。 如果计算的至少一个过程规范限制不允许可制造过程,则可以重新优化极限。