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1. 发明授权

US08098518B2 Nonvolatile memory device using variable resistive element 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US08098518B2
公开(公告)日：2012-01-17
申请号：US12476875
申请日：2009-06-02
申请人： Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
发明人： Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C8/10 , G11C13/00 , G11C13/0004 , G11C13/0026
摘要： A nonvolatile memory device may include a memory cell array with a plurality of nonvolatile memory cells arranged in an array of rows and columns. Each of a plurality of bit lines may be coupled to nonvolatile memory cells in a respective one of the columns of the array, and each of a plurality of column selection switches may be coupled to a respective one of the bit lines. A column decoder may be coupled to the plurality of column selection switches, and the column decoder may be configured to select a first one of the bit lines using a first column selection signal having a first signal level applied to a first one of the column selection switches. The column decoder may be further configured to select a second one of the bit lines using a second column selection signal having a second signal level applied to a second one of the column selection switches with the second signal level being different than the first signal level.
摘要翻译：非易失性存储器件可以包括具有排列成行和列阵列的多个非易失性存储单元的存储单元阵列。多个位线中的每一个可以耦合到阵列的各个列中的非易失性存储器单元，并且多个列选择开关中的每一个可以耦合到相应的一个位线。列解码器可以耦合到多个列选择开关，并且列解码器可以被配置为使用具有施加到列选择中的第一个的第一信号电平的第一列选择信号来选择位线中的第一位开关。列解码器还可以被配置为使用具有第二信号电平的第二列选择信号来选择位线中的第二位，其中第二信号电平施加到第二信号电平不同于第一信号电平的列选择开关中的第二信号电平。

2. 发明申请

US20090296459A1 Nonvolatile Memory Device Using Variable Resistive Element 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US20090296459A1
公开(公告)日：2009-12-03
申请号：US12476875
申请日：2009-06-02
申请人： Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
发明人： Hye-Jin Kim , Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C11/00 , G11C8/10 , G11C7/06
CPC分类号： G11C13/0023 , G11C8/10 , G11C13/00 , G11C13/0004 , G11C13/0026
摘要： A nonvolatile memory device may include a memory cell array with a plurality of nonvolatile memory cells arranged in an array of rows and columns. Each of a plurality of bit lines may be coupled to nonvolatile memory cells in a respective one of the columns of the array, and each of a plurality of column selection switches may be coupled to a respective one of the bit lines. A column decoder may be coupled to the plurality of column selection switches, and the column decoder may be configured to select a first one of the bit lines using a first column selection signal having a first signal level applied to a first one of the column selection switches. The column decoder may be further configured to select a second one of the bit lines using a second column selection signal having a second signal level applied to a second one of the column selection switches with the second signal level being different than the first signal level.
摘要翻译：非易失性存储器件可以包括具有排列成行和列阵列的多个非易失性存储单元的存储单元阵列。多个位线中的每一个可以耦合到阵列的各个列中的非易失性存储器单元，并且多个列选择开关中的每一个可以耦合到相应的一个位线。列解码器可以耦合到多个列选择开关，并且列解码器可以被配置为使用具有施加到列选择中的第一个的第一信号电平的第一列选择信号来选择位线中的第一位开关。列解码器还可以被配置为使用具有第二信号电平的第二列选择信号来选择位线中的第二位，其中第二信号电平施加到第二信号电平不同于第一信号电平的列选择开关中的第二信号电平。

3. 发明申请

US20070217273A1 PHASE-CHANGE RANDOM ACCESS MEMORY 有权
标题翻译：相变随机存取存储器
公开(公告)号：US20070217273A1
公开(公告)日：2007-09-20
申请号：US11616969
申请日：2006-12-28
申请人： Byung-Gil Choi , Du-Eung Kim , Woo-Yeong Cho , Hye-Jin Kim
发明人： Byung-Gil Choi , Du-Eung Kim , Woo-Yeong Cho , Hye-Jin Kim
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/02 , G11C29/027 , G11C29/787 , G11C29/804 , G11C29/846
摘要： A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.
摘要翻译：相变随机存取存储器包括存储块，该存储块包括对应于同一列地址的多个存储器列并使用不同的输入/输出路径; 冗余存储器块，其包括使用不同的输入/输出路径的多个冗余存储器列; 以及输入/输出控制器，其使用所述多个冗余存储器列中的至少一个来修复所述多个存储器列中的至少一个，并且响应于输入/输出修复模式来控制使用冗余存储器列同时修复的存储器列的数量控制信号。

4. 发明授权

US08085575B2 Nonvolatile memory device and method of driving the same 有权
标题翻译：非易失存储器件及其驱动方法
公开(公告)号：US08085575B2
公开(公告)日：2011-12-27
申请号：US12585728
申请日：2009-09-23
申请人： Byung-Gil Choi , Du-Eung Kim , Hye-Jin Kim
发明人： Byung-Gil Choi , Du-Eung Kim , Hye-Jin Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C7/02 , G11C7/12 , G11C7/18 , G11C13/00 , G11C13/0004 , G11C13/0026
摘要： A nonvolatile memory device and a method of driving the same are provided, which adopt an improved write operation. The method of driving a nonvolatile memory device includes providing the nonvolatile memory device including a plurality of memory banks each having a plurality of local bit lines and a plurality of variable resistance memory cells; selectively connecting read global bit lines for reading data with the local bit lines, and firstly discharging the selectively connected local bit lines by turning on local bit line discharge transistors coupled to the read global bit lines; and selectively connecting write global bit lines for writing data with the local bit lines, and secondly discharging the selectively connected local bit lines by turning on global bit line discharge transistors.
摘要翻译：提供一种非易失性存储器件及其驱动方法，其采用改进的写入操作。驱动非易失性存储器件的方法包括提供包括多个存储体的非易失性存储器件，每个存储器组具有多个局部位线和多个可变电阻存储器单元; 选择性地连接读取全局位线用于与局部位线一起读取数据，并且首先通过连接耦合到读出的全局位线的局部位线放电晶体管来放电选择性连接的局部位线; 并选择性地连接用于将数据写入本地位线的写入全局位线，以及其次通过导通全局位线放电晶体管对选择连接的局部位线进行放电。

5. 发明授权

US07729160B2 Phase-change random access memory 有权
标题翻译：相变随机存取存储器
公开(公告)号：US07729160B2
公开(公告)日：2010-06-01
申请号：US11616969
申请日：2006-12-28
申请人： Byung-Gil Choi , Du-Eung Kim , Woo-Yeong Cho , Hye-Jin Kim
发明人： Byung-Gil Choi , Du-Eung Kim , Woo-Yeong Cho , Hye-Jin Kim
IPC分类号： G11C11/00
CPC分类号： G11C29/808 , G11C29/02 , G11C29/027 , G11C29/787 , G11C29/804 , G11C29/846
摘要： A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.
摘要翻译：相变随机存取存储器包括存储块，该存储块包括对应于同一列地址的多个存储器列并使用不同的输入/输出路径; 冗余存储器块，其包括使用不同的输入/输出路径的多个冗余存储器列; 以及输入/输出控制器，其使用所述多个冗余存储器列中的至少一个来修复所述多个存储器列中的至少一个，并且响应于输入/输出修复模式来控制使用冗余存储器列同时修复的存储器列的数量控制信号。

6. 发明申请

US20100080039A1 Nonvoltile memory device and method of driving the same 有权
标题翻译：非挥发性记忆装置及其驱动方法
公开(公告)号：US20100080039A1
公开(公告)日：2010-04-01
申请号：US12585728
申请日：2009-09-23
申请人： Byung-Gil Choi , Du-Eung Kim , Hye-Jin Kim
发明人： Byung-Gil Choi , Du-Eung Kim , Hye-Jin Kim
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00 , G11C7/02
CPC分类号： G11C13/0023 , G11C7/02 , G11C7/12 , G11C7/18 , G11C13/00 , G11C13/0004 , G11C13/0026
摘要： A nonvolatile memory device and a method of driving the same are provided, which adopt an improved write operation. The method of driving a nonvolatile memory device includes providing the nonvolatile memory device including a plurality of memory banks each having a plurality of local bit lines and a plurality of variable resistance memory cells; selectively connecting read global bit lines for reading data with the local bit lines, and firstly discharging the selectively connected local bit lines by turning on local bit line discharge transistors coupled to the read global bit lines; and selectively connecting write global bit lines for writing data with the local bit lines, and secondly discharging the selectively connected local bit lines by turning on global bit line discharge transistors.
摘要翻译：提供一种非易失性存储器件及其驱动方法，其采用改进的写入操作。驱动非易失性存储器件的方法包括提供包括多个存储体的非易失性存储器件，每个存储器组具有多个局部位线和多个可变电阻存储器单元; 选择性地连接读取全局位线用于与局部位线一起读取数据，并且首先通过连接耦合到读出的全局位线的局部位线放电晶体管来放电选择性连接的局部位线; 并选择性地连接用于将数据写入本地位线的写入全局位线，以及其次通过导通全局位线放电晶体管对选择连接的局部位线进行放电。

7. 发明授权

US07961508B2 Phase-change random access memory 有权
标题翻译：相变随机存取存储器
公开(公告)号：US07961508B2
公开(公告)日：2011-06-14
申请号：US12771028
申请日：2010-04-30
申请人： Byung-Gil Choi , Du-Eung Kim , Woo-Yeong Cho , Hye-Jin Kim
发明人： Byung-Gil Choi , Du-Eung Kim , Woo-Yeong Cho , Hye-Jin Kim
IPC分类号： G11C11/00
CPC分类号： G11C29/808 , G11C29/02 , G11C29/027 , G11C29/787 , G11C29/804 , G11C29/846
摘要： A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.
摘要翻译：相变随机存取存储器包括存储块，该存储块包括对应于同一列地址的多个存储器列并使用不同的输入/输出路径; 冗余存储器块，其包括使用不同的输入/输出路径的多个冗余存储器列; 以及输入/输出控制器，其使用所述多个冗余存储器列中的至少一个来修复所述多个存储器列中的至少一个，并且响应于输入/输出修复模式来控制使用冗余存储器列同时修复的存储器列的数量控制信号。

8. 发明申请

US20100061146A1 Nonvolatile Memory Devices Including Variable Resistive Elements 有权
标题翻译：包括可变电阻元件的非易失性存储器件
公开(公告)号：US20100061146A1
公开(公告)日：2010-03-11
申请号：US12556787
申请日：2009-09-10
申请人： Byung-Gil Choi , Hye-Jin Kim
发明人： Byung-Gil Choi , Hye-Jin Kim
IPC分类号： G11C11/00 , G11C7/04 , G11C5/14
CPC分类号： G11C8/08 , G11C13/0004 , G11C13/0028 , G11C2213/72
摘要： A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of the matrix. A row decoder may be coupled to the plurality of word lines with the row decoder being configured to disable at least one of the word lines using a row bias having a level that is adjusted responsive to changes in temperature. Such a nonvolatile memory device may operate with reduced standby currents.
摘要翻译：非易失性存储器件可以包括存储单元阵列，该存储单元阵列具有以矩阵形式布置的多个非易失性存储单元，包括多行非易失性存储单元。多个字线中的每一个可以与矩阵的相应行的非易失性存储器单元耦合。行解码器可以耦合到多个字线，其中行解码器被配置为使用具有响应于温度变化来调整的电平的行偏置来禁用至少一个字线。这种非易失性存储器件可以以减少的待机电流工作。

9. 发明授权

US08228720B2 Nonvolatile memory devices including variable resistive elements 有权
标题翻译：包括可变电阻元件的非易失性存储器件
公开(公告)号：US08228720B2
公开(公告)日：2012-07-24
申请号：US12556787
申请日：2009-09-10
申请人： Byung-Gil Choi , Hye-Jin Kim
发明人： Byung-Gil Choi , Hye-Jin Kim
IPC分类号： G11C7/04 , G11C8/08 , G11C11/21 , G11C8/10
CPC分类号： G11C8/08 , G11C13/0004 , G11C13/0028 , G11C2213/72
摘要： A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of the matrix. A row decoder may be coupled to the plurality of word lines with the row decoder being configured to disable at least one of the word lines using a row bias having a level that is adjusted responsive to changes in temperature. Such a nonvolatile memory device may operate with reduced standby currents.
摘要翻译：非易失性存储器件可以包括存储单元阵列，该存储单元阵列具有以矩阵形式布置的多个非易失性存储单元，包括多行非易失性存储单元。多个字线中的每一个可以与矩阵的相应行的非易失性存储器单元耦合。行解码器可以耦合到多个字线，其中行解码器被配置为使用具有响应于温度变化调节的电平的行偏置来禁用至少一个字线。这种非易失性存储器件可以以减少的待机电流工作。

10. 发明授权

US08964488B2 Non-volatile memory device using variable resistance element with an improved write performance 有权
标题翻译：使用可变电阻元件的非易失性存储器件具有改进的写入性能
公开(公告)号：US08964488B2
公开(公告)日：2015-02-24
申请号：US13470617
申请日：2012-05-14
申请人： Hye-Jin Kim , Kwang-Jin Lee , Du-Eung Kim , Hung-Jun An
发明人： Hye-Jin Kim , Kwang-Jin Lee , Du-Eung Kim , Hung-Jun An
IPC分类号： G11C5/14 , G11C7/10 , G11C11/22 , G11C13/00 , G11C8/10
CPC分类号： G11C5/14 , G11C7/1078 , G11C7/1096 , G11C8/10 , G11C11/22 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/0088 , G11C2013/009 , G11C2213/72
摘要： A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator configured to generate a first voltage, a voltage pad configured to receive an external voltage that has a level higher than the first voltage, a write driver configured to be supplied with the external voltage and configured to write data to the plurality of non-volatile memory cells selected from the memory cell array; a sense amplifier configured to be supplied with the external voltage and configured to read data from the plurality of non-volatile memory cells selected from the memory cell array, and a row decoder and a column decoder configured to select the plurality of non-volatile memory cells included in the memory cell array, the row decoder being supplied with the first voltage and the column decoder being supplied with the external voltage.
摘要翻译：提供了使用可变电阻元件的非易失性存储器件。非易失性存储器件包括具有多个非易失性存储器单元的存储单元阵列，被配置为产生第一电压的第一电压发生器，被配置为接收具有高于第一电压的电平的外部电压的电压焊盘写入驱动器，被配置为被提供有所述外部电压并被配置为向从所述存储单元阵列中选择的所述多个非易失性存储器单元写入数据; 感测放大器，被配置为被提供有外部电压并且被配置为从从存储单元阵列中选择的多个非易失性存储器单元读取数据;行解码器和列解码器，被配置为选择多个非易失性存储器包括在存储单元阵列中的单元，行解码器被提供有第一电压，并且列解码器被提供有外部电压。

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