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    • 2. 发明申请
    • Ultra Low Power Transistor for 40nm Processes
    • 用于40nm工艺的超低功耗晶体管
    • US20150270367A1
    • 2015-09-24
    • US14560504
    • 2014-12-04
    • Cambridge Silicon Radio Limited
    • David VigarDave VerityRainer Herberholz
    • H01L29/66
    • H01L21/2658H01L21/26586H01L29/1083H01L29/66575H01L29/78
    • Methods of fabricating ultra-low power transistors are described using advanced technology nodes (e.g. 40 nm or less). In an embodiment, by optimizing a MOSFET to a different point, i.e. for low junction off (or leakage) current rather than speed/on current, a MOSFET can be produced which still meets the HCl reliability specification but has significantly reduced power consumption when off, e.g. half to one third of the standard off current. At this new optimisation point, the LDD dose is reduced to a level (e.g. 10-20% of the standard LDD dose) such that if it is reduced further, the device will no longer pass the HCl reliability specification. This is in contrast to standard MOSFETs which are optimized for speed/on current and have an LDD dose which, if increased further, would cause the device to no longer pass the HCl reliability specification.
    • 使用先进的技术节点(例如40nm或更小)来描述制造超低功率晶体管的方法。 在一个实施例中,通过将MOSFET优化到不同的点,即用于低接通(或泄漏)电流而不是速度/导通电流,可以生产仍然满足HCl可靠性规范的MOSFET,但是在关断时显着降低功耗 ,例如 标准关闭电流的一半到三分之一。 在这个新的优化点,LDD剂量降低到一个水平(例如标准LDD剂量的10-20%),这样,如果进一步降低,器件将不再通过HCl可靠性规范。 这与针对速度/导通电流进行了优化的标准MOSFET相反,并具有LDD剂量,如果进一步增加,则会导致器件不再通过HCl可靠性规范。
    • 4. 发明申请
    • INTEGRAL FABRICATION OF ASYMMETRIC CMOS TRANSISTORS FOR AUTONOMOUS WIRELESS STATE RADIOS AND SENSOR/ACTUATOR NODES
    • 用于自动无线状态无线电和传感器/执行器编号的不对称CMOS晶体管的集成制造
    • US20150213180A1
    • 2015-07-30
    • US14168665
    • 2014-01-30
    • CAMBRIDGE SILICON RADIO LIMITED
    • Rainer Herberholz
    • G06F17/50
    • G06F17/5072H01L21/823814H01L23/00H01L27/0207H01L27/092H01L29/1045H01L29/7835H01L2924/0002H01L2924/00
    • A method of arranging asymmetrically doped CMOS transistors in a semiconductor wafer that forms base cells within a plurality of logic standard cells in a CMOS process technology that includes conventional symmetric CMOS transistors having different threshold voltages. The asymmetrically doped CMOS transistors have a gate length exceeding 1.5 times the minimum gate length of the symmetric CMOS transistors. Regions defined by electrical junctions directly adjacent to the gate of the asymmetric transistors are formed by an implant mask exposing an area of the wafer on the source side of the transistor to receive the junction implant of the symmetric CMOS transistors with a higher threshold voltage while shielding the drain area, and a further implant mask exposing an area of the wafer on the drain side of the transistor to receive the junction implant of the symmetric CMOS transistors with a lower threshold voltage while shielding the source area.
    • 在半导体晶片中布置不对称掺杂的CMOS晶体管的方法,该半导体晶片在包括具有不同阈值电压的常规对称CMOS晶体管的CMOS工艺技术中在多个逻辑标准单元内形成基本单元。 非对称掺杂的CMOS晶体管的栅极长度超过对称CMOS晶体管的最小栅极长度的1.5倍。 由不对称晶体管的栅极直接相邻的电接点限定的区域由在晶体管的源极侧暴露晶片的区域的注入掩模形成,以接收具有较高阈值电压的对称CMOS晶体管的结注入,同时屏蔽 漏极区域和另外的植入掩模,暴露晶体管的漏极侧的晶片的区域,以在屏蔽源极区域的同时接收具有较低阈值电压的对称CMOS晶体管的结注入。