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1. 发明授权

US09595670B1 Resistive random access memory (RRAM) cell and method for forming the RRAM cell 有权
标题翻译：电阻随机存取存储器（RRAM）单元及形成RRAM单元的方法
公开(公告)号：US09595670B1
公开(公告)日：2017-03-14
申请号：US14337111
申请日：2014-07-21
申请人： Crossbar, Inc.
发明人： Harry Yue Gee , Steven Patrick Maxwell , Natividad Vasquez, Jr. , Sundar Narayanan
IPC分类号： H01L21/336 , H01L45/00
CPC分类号： H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/1675
摘要： A method includes patterning a layered structure comprising a monolithic stack including a bottom electrode surrounded by a dielectric material, a switching material, a barrier material, a dielectric hardmask, and a patterned photoresist formed above and adjacent to a portion of the dielectric hardmask. The patterning includes patterning the dielectric hardmask using a first etchant and employing the patterned photoresist as a mask, patterning the barrier material using a second etchant and employing a portion of the dielectric hardmask remaining after the patterning the dielectric hardmask as a mask, and patterning the switching material using ion milling or etching and employing the portion of the dielectric hardmask remaining after the patterning the barrier material as a mask.
摘要翻译：一种方法包括图案化的层状结构，其包括单片堆叠，其包括由介电材料包围的底部电极，开关材料，阻挡材料，电介质硬掩模和形成在电介质硬掩模的一部分上方并与其相邻的图案化光致抗蚀剂。图案化包括使用第一蚀刻剂图案化介电硬掩模，并使用图案化的光致抗蚀剂作为掩模，使用第二蚀刻剂图案化阻挡材料，并且在图案化介电硬掩模作为掩模之后使用剩余的介电硬掩模的一部分，使用离子研磨或蚀刻的开关材料，并且在将阻挡材料图案化为掩模之后使用剩余的电介质硬掩模的部分。

2. 发明授权

US10290801B2 Scalable silicon based resistive memory device 有权
公开(公告)号：US10290801B2
公开(公告)日：2019-05-14
申请号：US14613585
申请日：2015-02-04
申请人： Crossbar, Inc.
发明人： Sundar Narayanan , Steve Maxwell , Natividad Vasquez, Jr. , Harry Yue Gee
IPC分类号： H01L45/00 , H01L27/24
摘要： A memory cell that includes a first metal layer formed over a substrate is provided. The substrate includes one or more complementary metal-oxide semiconductor devices. The memory cell also includes a via device that connects at least a portion of the first metal layer and at least another portion of a second metal layer. The first metal layer has a first thickness having an edge thereof that serves as an electrode for a memory cell formed by the via device. The memory cell scales as a function of the first thickness and at least in part independent of a minimum feature size of the memory device.

3. 发明授权

US10096653B2 Monolithically integrated resistive memory using integrated-circuit foundry compatible processes 有权
公开(公告)号：US10096653B2
公开(公告)日：2018-10-09
申请号：US14587711
申请日：2014-12-31
申请人： Crossbar, Inc.
发明人： Sundar Narayanan , Steve Maxwell , Natividad Vasquez, Jr. , Harry Yue Gee
IPC分类号： H01L21/00 , H01L27/24 , H01L45/00 , H01L27/092
摘要： Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

4. 发明申请

US20220320429A1 RESISTIVE SWITCHING MEMORY DEVICES AND METHOD(S) FOR FORMING THE RESISTIVE SWITCHING MEMORY DEVICES 有权
公开(公告)号：US20220320429A1
公开(公告)日：2022-10-06
申请号：US17218624
申请日：2021-03-31
申请人： CROSSBAR, INC.
发明人： Sundar Narayanan , Wee Chen Gan , Natividad Vasquez, Jr.
IPC分类号： H01L45/00 , H01L27/24
摘要： Fabrication of resistive switching memory devices is herein provided. By way of example, a method for a two-step etch for fabricating a non-volatile resistive memory device is disclosed. In another example, a method for a three-step etch for fabricating a non-volatile resistive memory device is provided. Still other embodiments disclose a method for fabricating a non-volatile metal nitrogen/metal oxygen resistive switching memory device. Further embodiments disclose a method for fabricating a volatile resistive switching selector device. Processes for forming protective spacers in conjunction with fabricating a disclosed resistive memory device are also provided.

5. 发明授权

US10115819B2 Recessed high voltage metal oxide semiconductor transistor for RRAM cell 有权
公开(公告)号：US10115819B2
公开(公告)日：2018-10-30
申请号：US14726071
申请日：2015-05-29
申请人： Crossbar, Inc.
发明人： Harry Yue Gee , Tanmay Kumar , Natividad Vasquez, Jr. , Steven Patrick Maxwell , Sundar Narayanan
IPC分类号： H01L29/423 , H01L27/24 , H01L29/78 , H01L45/00 , H01L29/66
摘要： A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.

6. 发明授权

US09583701B1 Methods for fabricating resistive memory device switching material using ion implantation 有权
标题翻译：使用离子注入制造电阻式存储器件开关材料的方法
公开(公告)号：US09583701B1
公开(公告)日：2017-02-28
申请号：US14213953
申请日：2014-03-14
申请人： Crossbar, Inc.
发明人： Harry Yue Gee , Steven Patrick Maxwell , Natividad Vasquez, Jr. , Mark Harold Clark
IPC分类号： H01L45/00
CPC分类号： H01L45/1266 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1675
摘要： A memory device comprising a doped conductive polycrystalline layer having an electrically resistive portion, is described herein. By way of example, ion implantation to a subset of the conductive polycrystalline layer can degrade and modify the polycrystalline layer, forming the electrically resistive portion. The electrically resistive portion can include resistive switching properties facilitating digital information storage. Parametric control of the ion implantation can facilitate control over corresponding resistive switching properties of the resistive portion. For example, a projected range or depth of the ion implantation can be controlled, allowing for preferential placement of atoms in the resistive portion, and fine-tuning of a forming voltage of the memory device. As another example, dose and number of atoms implanted, type of atoms or ions that are implanted, the conductive polycrystalline material used, and so forth, can facilitate control over switching characteristics of the memory device.
摘要翻译：本文描述了包括具有电阻部分的掺杂导电多晶层的存储器件。作为示例，离子注入导电多晶层的子集可以降解和修饰多晶层，从而形成电阻部分。电阻部分可以包括促进数字信息存储的电阻切换特性。离子注入的参数控制可以有助于控制电阻部分的对应的电阻开关特性。例如，可以控制离子注入的投影范围或深度，允许优先放置电阻部分中的原子，以及微调存储器件的形成电压。作为另一示例，注入的原子的剂量和数量，注入的原子或离子的类型，使用的导电多晶材料等等可以有助于对存储器件的开关特性的控制。

7. 发明授权

US09741765B1 Monolithically integrated resistive memory using integrated-circuit foundry compatible processes 有权
公开(公告)号：US09741765B1
公开(公告)日：2017-08-22
申请号：US14588136
申请日：2014-12-31
申请人： Crossbar, Inc.
发明人： Sundar Narayanan , Steve Maxwell , Natividad Vasquez, Jr. , Harry Yue Gee
IPC分类号： H01L27/092 , H01L45/00 , H01L27/24
CPC分类号： H01L27/2463 , H01L27/092 , H01L27/2436 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/148 , H01L45/16
摘要： Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

8. 发明授权

US09437814B1 Mitigating damage from a chemical mechanical planarization process 有权
标题翻译：减轻化学机械平面化过程造成的损害
公开(公告)号：US09437814B1
公开(公告)日：2016-09-06
申请号：US14473879
申请日：2014-08-29
申请人： Crossbar, Inc.
发明人： Harry Yue Gee , Majid Milani , Natividad Vasquez, Jr. , Steven Patrick Maxwell , Sundar Narayanan
IPC分类号： H01L21/332 , H01L45/00
CPC分类号： H01L45/16 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/145
摘要： During fabrication of a two-terminal memory device, a terminal (e.g., bottom terminal) can be formed. After formation of the terminal, a chemical mechanical planarization (CMP) process can be applied that, depending on the composition of the terminal, can cause damage that affect operating characteristics of the finished memory device or cell. In some embodiments, such damage can be removed by one or more post-CMP processes. In some embodiments, such damage can be mitigated so as to prevent the damage from occurring at all, by, e.g., forming a sacrificial layer atop the terminal prior to performing the CMP process. Thus, the sacrificial layer can operate to protect the terminal from damage resulting from the CMP process, with the remainder of the sacrificial layer being removed prior to completing the fabrication of the two-terminal memory device.
摘要翻译：在制造双端存储器件期间，可以形成端子（例如，底端）。在端子形成之后，可以应用化学机械平面化（CMP）工艺，根据端子的组成，可以引起影响成品存储器件或电池的工作特性的损坏。在一些实施例中，可以通过一个或多个后CMP工艺来去除这种损伤。在一些实施例中，可以减轻这种损害，以便防止在完成CMP过程之前通过例如在端子顶部形成牺牲层来完全发生损坏。因此，牺牲层可以操作以保护端子免受由CMP工艺引起的损伤，在完成两端存储器件的制造之前牺牲层的其余部分被去除。

9. 发明授权

US09166163B2 Sub-oxide interface layer for two-terminal memory 有权
标题翻译：二氧化硅接口层用于双端存储器
公开(公告)号：US09166163B2
公开(公告)日：2015-10-20
申请号：US14027045
申请日：2013-09-13
申请人： Crossbar, Inc.
发明人： Harry Yue Gee , Mark Harold Clark , Steven Patrick Maxwell , Sung Hyun Jo , Natividad Vasquez, Jr.
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L45/085 , H01L27/2436 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1608 , H01L45/1633
摘要： Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.
摘要翻译：本文描述了提供双端存储器件的制造，构造和/或组装。双端存储器件可以包括具有硅轴承层，界面层和活性金属层的有源区。可以创建界面层，其包括可以是具有聚集化学式SiO x的多个硅和/或氧化硅层的组合的非重质亚氧化物，其中X可以是大于零且小于2的非整数亚氧化物可以以各种方式产生，包括与生长亚氧化物，沉积亚氧化物或将现有薄膜转化为亚氧化物相关的各种技术。

10. 发明授权

US10319908B2 Integrative resistive memory in backend metal layers 有权
公开(公告)号：US10319908B2
公开(公告)日：2019-06-11
申请号：US14636363
申请日：2015-03-03
申请人： Crossbar, Inc.
发明人： Sundar Narayanan , Steve Maxwell , Natividad Vasquez, Jr. , Harry Yue Gee
IPC分类号： H01L45/00 , H01L27/24 , H01L23/522 , H01L21/768 , H01L23/532 , H01L27/10 , H01L27/092
摘要： Providing for a memory device having a resistive switching memory integrated within backend layers of the memory device is described herein. By way of example, the resistive switching memory can be embedded memory such as cache, random access memory, or the like, in various embodiments. The resistive memory can be fabricated between various backend metallization schemes, including backend copper metal layers and in part utilizing one or more damascene processes. In some embodiments, the resistive memory can be fabricated in part with damascene processes and in part with subtractive etch processing, utilizing four or fewer photo-resist masks. Accordingly, the disclosure provides a relatively low cost, high performance embedded memory compatible with a variety of fabrication processes of integrated circuit foundries.

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