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1. 发明授权

US09280614B1 Methods, systems, and apparatus for clock topology planning with reduced power consumption 有权
标题翻译：时钟拓扑规划的方法，系统和设备，降低功耗
公开(公告)号：US09280614B1
公开(公告)日：2016-03-08
申请号：US13844764
申请日：2013-03-15
申请人： Cadence Design Systems, Inc.
发明人： Ankush Sood , Aaron Paul Hurst
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5072 , G06F2217/62 , G06F2217/84
摘要： In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.
摘要翻译：在本发明的一个实施例中，公开了一种用于设计集成电路的物理时钟拓扑规划的方法。该方法包括读取集成电路设计的初始放置网表和集成电路设计的平面图，分析集成电路设计以确定对多个触发器进行时钟以降低功耗的栅时钟信号的潜在使能信号; 同时优化并将时钟使能逻辑门施加到多个触发器的门时钟信号; 并使时钟信号的定时变化最小化到多个触发器。

2. 发明授权

US09135375B1 Methods for construction and optimization of a clock tree plan for reduced power consumption 有权
标题翻译：用于降低功耗的时钟树计划的构建和优化方法
公开(公告)号：US09135375B1
公开(公告)日：2015-09-15
申请号：US13815902
申请日：2013-03-15
申请人： Cadence Design Systems, Inc.
发明人： Ankush Sood , Aaron Paul Hurst
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/50 , G06F17/5072 , G06F2217/62 , G06F2217/84
摘要： In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.
摘要翻译：在本发明的一个实施例中，公开了一种用于设计集成电路的物理时钟拓扑规划的方法。该方法包括读取集成电路设计的初始放置网表和集成电路设计的平面图，分析集成电路设计以确定对多个触发器进行时钟以降低功耗的栅时钟信号的潜在使能信号; 同时优化并将时钟使能逻辑门施加到多个触发器的门时钟信号; 并使时钟信号的定时变化最小化到多个触发器。

3. 发明授权

US09411912B1 Clock topology planning for reduced power consumption 有权
标题翻译：时钟拓扑规划，降低功耗
公开(公告)号：US09411912B1
公开(公告)日：2016-08-09
申请号：US13844683
申请日：2013-03-15
申请人： Cadence Design Systems, Inc.
发明人： Ankush Sood , Aaron Paul Hurst
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5072 , G06F2217/62 , G06F2217/84
摘要： In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.
摘要翻译：在本发明的一个实施例中，公开了一种用于设计集成电路的物理时钟拓扑规划的方法。该方法包括读取集成电路设计的初始放置网表和集成电路设计的平面图，分析集成电路设计以确定对多个触发器进行时钟以降低功耗的栅时钟信号的潜在使能信号; 同时优化并将时钟使能逻辑门施加到多个触发器的门时钟信号; 并使时钟信号的定时变化最小化到多个触发器。

4. 发明授权

US08826211B1 Graphical user interface for physically aware clock tree planning 有权
标题翻译：用于物理感知时钟树规划的图形用户界面
公开(公告)号：US08826211B1
公开(公告)日：2014-09-02
申请号：US13839769
申请日：2013-03-15
申请人： Cadence Design Systems, Inc.
发明人： Ankush Sood , Aaron Paul Hurst
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/62 , G06F2217/74
摘要： In one embodiment of the invention, a method for displaying and analyzing a clock gate tree topology is disclosed. The method includes displaying a bounding box of each flip-flop cluster in the floor plan of the integrated circuit; and for each flip-flop cluster, calculating the coordinates for a center of mass of the flip-flop cluster, displaying the position of the clock gate driving the flip-flops in the flip-flop cluster with respect to the center of mass of the flip-flop cluster, displaying first air lines from the enable signal gate to the clock gate with a first color, and displaying second air lines from the clock gate to the center of mass of the flip-flop cluster with a second color differing from the first color.
摘要翻译：在本发明的一个实施例中，公开了一种用于显示和分析时钟门树拓扑的方法。该方法包括在集成电路的平面图中显示每个触发器簇的边界框; 并且对于每个触发器簇，计算触发器簇的质心的坐标，显示相对于触发器簇的质心显示驱动触发器组中的触发器的时钟栅极的位置触发器组，用第一颜色将使能信号门的第一空气线路显示到时钟门，并且以不同于第二颜色的第二颜色将第二空气线从时钟门显示到触发器簇的质心第一种颜色

5. 发明授权

US08782591B1 Physically aware logic synthesis of integrated circuit designs 有权
标题翻译：集成电路设计的物理意识逻辑综合
公开(公告)号：US08782591B1
公开(公告)日：2014-07-15
申请号：US13732364
申请日：2012-12-31
申请人： Cadence Design Systems, Inc.
发明人： Tsuwei Ku , David Seibert , Huey-Yih Wang , Hua Song , Kai Zhu , Yu-Fang Chung , Ankush Sood
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： In one embodiment of the invention, a method of synthesizing physical gates from register transfer logic code for an integrated circuit design is disclosed. The method includes reading a register transfer level (RTL) input file describing an integrated circuit design; parsing and translating the RTL input file into a plurality of Boolean logic equations; translating the plurality of Boolean logic equations into a plurality of logic primitives; placing the plurality of logic primitives into a floorplan of the integrated circuit design, wherein the placement of the plurality of logic primitives defines wire interconnects; and optimizing each of the plurality of Boolean logic equations in response to wire costs and wire timing delays.
摘要翻译：在本发明的一个实施例中，公开了一种从用于集成电路设计的寄存器传送逻辑代码合成物理门的方法。该方法包括读取描述集成电路设计的寄存器传送级（RTL）输入文件; 将RTL输入文件解析和翻译成多个布尔逻辑方程; 将所述多个布尔逻辑方程转换成多个逻辑基元; 将所述多个逻辑图元放置在所述集成电路设计的平面图中，其中所述多个逻辑图元的布置定义了线互连; 以及响应于电线成本和有线定时延迟优化所述多个布尔逻辑方程中的每一个。

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