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1. 发明授权

US08782591B1 Physically aware logic synthesis of integrated circuit designs 有权
标题翻译：集成电路设计的物理意识逻辑综合
公开(公告)号：US08782591B1
公开(公告)日：2014-07-15
申请号：US13732364
申请日：2012-12-31
申请人： Cadence Design Systems, Inc.
发明人： Tsuwei Ku , David Seibert , Huey-Yih Wang , Hua Song , Kai Zhu , Yu-Fang Chung , Ankush Sood
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： In one embodiment of the invention, a method of synthesizing physical gates from register transfer logic code for an integrated circuit design is disclosed. The method includes reading a register transfer level (RTL) input file describing an integrated circuit design; parsing and translating the RTL input file into a plurality of Boolean logic equations; translating the plurality of Boolean logic equations into a plurality of logic primitives; placing the plurality of logic primitives into a floorplan of the integrated circuit design, wherein the placement of the plurality of logic primitives defines wire interconnects; and optimizing each of the plurality of Boolean logic equations in response to wire costs and wire timing delays.
摘要翻译：在本发明的一个实施例中，公开了一种从用于集成电路设计的寄存器传送逻辑代码合成物理门的方法。该方法包括读取描述集成电路设计的寄存器传送级（RTL）输入文件; 将RTL输入文件解析和翻译成多个布尔逻辑方程; 将所述多个布尔逻辑方程转换成多个逻辑基元; 将所述多个逻辑图元放置在所述集成电路设计的平面图中，其中所述多个逻辑图元的布置定义了线互连; 以及响应于电线成本和有线定时延迟优化所述多个布尔逻辑方程中的每一个。

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