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1. 发明授权

US07848149B2 Reducing the effects of noise in non-volatile memories through multiple reads 有权
标题翻译：通过多次读取降低非易失性存储器中噪声的影响
公开(公告)号：US07848149B2
公开(公告)日：2010-12-07
申请号：US11674000
申请日：2007-02-12
申请人： Carlos J. Gonzalez , Daniel C. Guterman
发明人： Carlos J. Gonzalez , Daniel C. Guterman
IPC分类号： G11C11/34
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1051 , G11C16/12 , G11C16/26 , G11C16/28 , G11C16/3454 , G11C16/3459 , G11C2013/0057
摘要： Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics. A similar form of signal averaging may be employed during the verify phase of programming. An embodiment of this technique would use a peak-detection scheme. In this scenario, several verify checks are performed at the state prior to deciding if the storage element has reached the target state. If some predetermined portion of the verifies fail, the storage element receives additional programming. These techniques allow the system to store more states per storage element in the presence of various sources of noise.
摘要翻译：存储元件被读取多次，并且对于每个存储元件累积和平均结果，以减少可能不利地影响读取质量的存储元件和相关电路中的噪声或其他瞬变的影响。可以采用几种技术，其中包括：由控制器对平均数据进行每次迭代从存储设备到控制器设备的完整读取和传输; 对每次迭代的数据进行完全读取，并由存储设备进行平均，并且在获得最终结果之前不转移到控制器; 一次完全读取，然后利用已建立的状态信息进行多次更快的重新读取，以避免完全读取，随后是引导存储元件被感测的状态的智能算法。这些技术可以用作正常操作模式，或者根据异常情况被调用，这取决于系统特性。可以在编程的验证阶段期间采用类似形式的信号平均。该技术的实施例将使用峰值检测方案。在这种情况下，在决定存储元件是否达到目标状态之前，先在状态下执行多个验证检查。如果验证的一些预定部分失败，则存储元件接收另外的编程。这些技术允许系统在存在各种噪声源的情况下存储每个存储元件的更多状态。

2. 发明授权

US06972993B2 Method and structure for efficient data verification operation for non-volatile memories 有权
标题翻译：用于非易失性存储器的有效数据验证操作的方法和结构
公开(公告)号：US06972993B2
公开(公告)日：2005-12-06
申请号：US10360829
申请日：2003-02-07
申请人： Kevin M. Conley , Daniel C. Guterman , Carlos J. Gonzalez
发明人： Kevin M. Conley , Daniel C. Guterman , Carlos J. Gonzalez
IPC分类号： G11C16/02 , G11C11/15 , G11C13/00 , G11C16/06 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2216/14
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations. The post-writer verification can be repeated and use different bias conditions for reading the data. The process can be automatic or executed by command that can specify the read conditions.
摘要翻译：改进的基于闪存EEPROM存储器的存储子系统包括一个或多个闪存阵列，每个闪存阵列具有三个数据寄存器和一个控制器电路。在闪存编程操作期间，使用一个数据寄存器来控制程序操作，第二个寄存器用于保存目标数据值，第三个寄存器用于加载下一个扇区的数据。在闪存编程操作之后，将扇区的数据从闪存阵列读入第一数据寄存器并与存储在第二寄存器中的目标数据进行比较。当数据验证良好时，来自第三寄存器的数据被复制到第一和第二寄存器用于下一个程序操作。这创建了一个改进的性能系统，在程序操作完成后需要数据验证的程序操作期间不会遭受数据传输延迟。替代实施例使用两个寄存器实现和单个寄存器实现来执行比较。可以重复写入后验证，并使用不同的偏置条件读取数据。该过程可以是自动的，也可以通过可以指定读取条件的命令执行。

3. 发明授权

US08473813B2 Methods of cell population distribution assisted read margining 有权
标题翻译：细胞群体分布的方法辅助读取边缘
公开(公告)号：US08473813B2
公开(公告)日：2013-06-25
申请号：US12984505
申请日：2011-01-04
申请人： Carlos J. Gonzalez , Daniel C. Guterman
发明人： Carlos J. Gonzalez , Daniel C. Guterman
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C16/04 , G11C16/26 , G11C16/3418 , G11C16/3422 , G11C29/028 , G11C29/42 , G11C29/46 , G11C29/50004 , G11C2029/0409 , G11C2029/0411
摘要： A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental evaluations, the memory device determines the read conditions at which to best decide the data stored.
摘要翻译：提出了当存储状态的分布降级时使用技术来提取其存储元件的数据内容的存储器。如果存储状态的分布已经降级，则使用修改的读取条件来执行存储器单元的二次评估。基于这些补充评估的结果，存储器件确定最佳地确定存储的数据的读取条件。

4. 发明申请

US20080077842A1 Memory with Cell Population Distribution Assisted Read Margining 有权
标题翻译：记忆与细胞人口分布辅助阅读保证金
公开(公告)号：US20080077842A1
公开(公告)日：2008-03-27
申请号：US11535879
申请日：2006-09-27
申请人： Carlos J. Gonzalez , Daniel C. Guterman
发明人： Carlos J. Gonzalez , Daniel C. Guterman
IPC分类号： G11C29/00
CPC分类号： G11C16/349 , G11C16/04 , G11C2029/0411
摘要： A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental evaluations, the memory device determines the read conditions at which to best decide the data stored.
摘要翻译：提出了当存储状态的分布降级时使用技术来提取其存储元件的数据内容的存储器。如果存储状态的分布已经降级，则使用修改的读取条件来执行存储器单元的二次评估。基于这些补充评估的结果，存储器件确定最佳地确定存储的数据的读取条件。

5. 发明授权

US07170782B2 Method and structure for efficient data verification operation for non-volatile memories 有权
标题翻译：用于非易失性存储器的有效数据验证操作的方法和结构
公开(公告)号：US07170782B2
公开(公告)日：2007-01-30
申请号：US11125644
申请日：2005-05-09
申请人： Kevin M. Conley , Daniel C. Guterman , Carlos J. Gonzalez
发明人： Kevin M. Conley , Daniel C. Guterman , Carlos J. Gonzalez
IPC分类号： G11C16/04 , G11C14/00
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2216/14
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations. The post-writer verification can be repeated and use different bias conditions for reading the data. The process can be automatic or executed by command that can specify the read conditions.
摘要翻译：改进的基于闪存EEPROM存储器的存储子系统包括一个或多个闪存阵列，每个闪存阵列具有三个数据寄存器和一个控制器电路。在闪存编程操作期间，使用一个数据寄存器来控制程序操作，第二个寄存器用于保存目标数据值，第三个寄存器用于加载下一个扇区的数据。在闪存编程操作之后，将扇区的数据从闪存阵列读入第一数据寄存器并与存储在第二寄存器中的目标数据进行比较。当数据验证良好时，来自第三寄存器的数据被复制到第一和第二寄存器用于下一个程序操作。这创建了一个改进的性能系统，在程序操作完成后需要数据验证的程序操作期间不会遭受数据传输延迟。替代实施例使用两个寄存器实现和单个寄存器实现来执行比较。可以重复写入后验证，并使用不同的偏置条件读取数据。该过程可以是自动的，也可以通过可以指定读取条件的命令执行。

6. 发明授权

US06952365B2 Reducing the effects of noise in non-volatile memories through multiple reads 失效
标题翻译：通过多次读取降低非易失性存储器中噪声的影响
公开(公告)号：US06952365B2
公开(公告)日：2005-10-04
申请号：US10799416
申请日：2004-03-12
申请人： Carlos J. Gonzalez , Daniel C. Guterman
发明人： Carlos J. Gonzalez , Daniel C. Guterman
IPC分类号： G11C16/02 , G11B5/09 , G11C7/08 , G11C7/10 , G11C16/26 , G11C16/28 , G11C16/34 , G11C11/34
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1051 , G11C16/12 , G11C16/26 , G11C16/28 , G11C16/3454 , G11C16/3459 , G11C2013/0057
摘要： Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics. A similar form of signal averaging may be employed during the verify phase of programming. An embodiment of this technique would use a peak-detection scheme. In this scenario, several verify checks are performed at the state prior to deciding if the storage element has reached the target state. If some predetermined portion of the verifies fail, the storage element receives additional programming. These techniques allow the system to store more states per storage element in the presence of various sources of noise.
摘要翻译：存储元件被读取多次，并且对于每个存储元件累积和平均结果，以减少可能不利地影响读取质量的存储元件和相关电路中的噪声或其他瞬变的影响。可以采用几种技术，其中包括：由控制器对平均数据进行每次迭代从存储设备到控制器设备的完整读取和传输; 对每次迭代的数据进行完全读取，并由存储设备进行平均，并且在获得最终结果之前不转移到控制器; 一次完全读取，然后利用已建立的状态信息进行多次更快的重新读取，以避免完全读取，随后是引导存储元件被感测的状态的智能算法。这些技术可以用作正常操作模式，或者根据异常情况被调用，这取决于系统特性。可以在编程的验证阶段期间采用类似形式的信号平均。该技术的实施例将使用峰值检测方案。在这种情况下，在决定存储元件是否达到目标状态之前，先在状态下执行多个验证检查。如果验证的一些预定部分失败，则存储元件接收另外的编程。这些技术允许系统在存在各种噪声源的情况下存储每个存储元件的更多状态。

7. 发明申请

US20110099438A1 Methods of Cell Population Distribution Assisted Read Margining 有权
标题翻译：细胞群体分布辅助读取边缘的方法
公开(公告)号：US20110099438A1
公开(公告)日：2011-04-28
申请号：US12984505
申请日：2011-01-04
申请人： Carlos J. Gonzalez , Daniel C. Guterman
发明人： Carlos J. Gonzalez , Daniel C. Guterman
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/50 , G11C16/04 , G11C16/26 , G11C16/3418 , G11C16/3422 , G11C29/028 , G11C29/42 , G11C29/46 , G11C29/50004 , G11C2029/0409 , G11C2029/0411
摘要： A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental evaluations, the memory device determines the read conditions at which to best decide the data stored.
摘要翻译：提出了当存储状态的分布降级时使用技术来提取其存储元件的数据内容的存储器。如果存储状态的分布已经降级，则使用修改的读取条件来执行存储器单元的二次评估。基于这些补充评估的结果，存储器件确定最佳地确定存储的数据的读取条件。

8. 发明授权

US07392358B2 Delivery of a message to a user of a portable data storage device as a condition of its use 有权
标题翻译：向便携式数据存储设备的用户传递消息作为其使用的条件
公开(公告)号：US07392358B2
公开(公告)日：2008-06-24
申请号：US11035701
申请日：2005-01-14
申请人： Jian Chen , Carlos J. Gonzalez , Daniel C. Guterman
发明人： Jian Chen , Carlos J. Gonzalez , Daniel C. Guterman
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F3/00 , G06F5/00 , G06Q30/00 , G07G1/14
CPC分类号： G06F12/1433 , G06F21/78 , G06F21/79 , G06F2221/2141 , G06Q30/0207 , G06Q30/0277
摘要： A memory card, flash memory drive or other removable re-programmable non-volatile memory device is configured so that at least part of the memory is not available for storage of user data until data of a message stored in the memory is at least read out by the user through a host device to which the memory device is connected. The message may be an advertisement, instructions on using the memory device, or the like, to which the user is at least exposed as a condition of having the full capacity of the memory card available thereafter for use by him or her.
摘要翻译：配置存储卡，闪速存储器驱动器或其他可移动可重新编程的非易失性存储器件，使得至少部分存储器不可用于存储用户数据，直到存储在存储器中的消息的数据至少被读出由用户通过与存储设备连接的主机设备。该消息可以是用户至少暴露于其中的广告，关于使用存储设备的指示等等，作为具有可供其使用的存储卡的全部容量的条件。

9. 发明授权

US07177195B2 Reducing the effects of noise in non-volatile memories through multiple reads 有权
标题翻译：通过多次读取降低非易失性存储器中噪声的影响
公开(公告)号：US07177195B2
公开(公告)日：2007-02-13
申请号：US11191823
申请日：2005-07-27
申请人： Carlos J. Gonzalez , Daniel C. Guterman
发明人： Carlos J. Gonzalez , Daniel C. Guterman
IPC分类号： G11C11/34
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1051 , G11C16/12 , G11C16/26 , G11C16/28 , G11C16/3454 , G11C16/3459 , G11C2013/0057
摘要： Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics. A similar form of signal averaging may be employed during the verify phase of programming. An embodiment of this technique would use a peak-detection scheme. In this scenario, several verify checks are performed at the state prior to deciding if the storage element has reached the target state. If some predetermined portion of the verifies fail, the storage element receives additional programming. These techniques allow the system to store more states per storage element in the presence of various sources of noise.
摘要翻译：存储元件被读取多次，并且对于每个存储元件累积和平均结果，以减少可能不利地影响读取质量的存储元件和相关电路中的噪声或其他瞬变的影响。可以采用几种技术，其中包括：由控制器对平均数据进行每次迭代从存储设备到控制器设备的完整读取和传输; 对每次迭代的数据进行完全读取，并由存储设备进行平均，并且在获得最终结果之前不转移到控制器; 一次完全读取，然后利用已建立的状态信息进行多次更快的重新读取，以避免完全读取，随后是引导存储元件被感测的状态的智能算法。这些技术可以用作正常操作模式，或者根据异常情况被调用，这取决于系统特性。可以在编程的验证阶段期间采用类似形式的信号平均。该技术的实施例将使用峰值检测方案。在这种情况下，在决定存储元件是否达到目标状态之前，先在状态下执行多个验证检查。如果验证的一些预定部分失败，则存储元件接收另外的编程。这些技术允许系统在存在各种噪声源的情况下存储每个存储元件的更多状态。

10. 发明授权

US06560143B2 Method and structure for efficient data verification operation for non-volatile memories 有权
标题翻译：用于非易失性存储器的有效数据验证操作的方法和结构
公开(公告)号：US06560143B2
公开(公告)日：2003-05-06
申请号：US10040748
申请日：2001-12-28
申请人： Kevin M. Conley , Daniel C. Guterman , Carlos J. Gonzalez
发明人： Kevin M. Conley , Daniel C. Guterman , Carlos J. Gonzalez
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2216/14
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations. The post-writer verification can be repeated and use different bias conditions for reading the data. The process can be automatic or executed by command that can specify the read conditions.
摘要翻译：改进的基于闪存EEPROM存储器的存储子系统包括一个或多个闪存阵列，每个闪存阵列具有三个数据寄存器和一个控制器电路。在闪存编程操作期间，使用一个数据寄存器来控制程序操作，第二个寄存器用于保存目标数据值，第三个寄存器用于加载下一个扇区的数据。在闪存编程操作之后，将扇区的数据从闪存阵列读入第一数据寄存器并与存储在第二寄存器中的目标数据进行比较。当数据验证良好时，来自第三寄存器的数据被复制到第一和第二寄存器用于下一个程序操作。这创建了一个改进的性能系统，在程序操作完成后需要数据验证的程序操作期间不会遭受数据传输延迟。替代实施例使用两个寄存器实现和单个寄存器实现来执行比较。可以重复写入后验证，并使用不同的偏置条件读取数据。该过程可以是自动的，也可以通过可以指定读取条件的命令执行。

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