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1. 发明授权

US09070583B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09070583B2
公开(公告)日：2015-06-30
申请号：US13230787
申请日：2011-09-12
申请人： Chang Youn Hwang
发明人： Chang Youn Hwang
IPC分类号： H01L29/72 , H01L27/108 , H01L21/768
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10855
摘要： Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern.
摘要翻译：提供半导体器件和制造半导体存储器件的方法。通过湿蚀刻形成接触塞。 SAC的长宽比降低，SAC故障降低，从而保证了处理余量。半导体器件包括半导体衬底，其包括有源区和限定有源区的器件隔离层，形成在半导体衬底上的导电图案，以及在半导体衬底上垂直于导电图案形成的氮化物层。

2. 发明授权

US07842593B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07842593B2
公开(公告)日：2010-11-30
申请号：US11771478
申请日：2007-06-29
申请人： Chang Youn Hwang , Hyun Ahn
发明人： Chang Youn Hwang , Hyun Ahn
IPC分类号： H01L21/3205
CPC分类号： H01L21/76897 , H01L21/3065 , H01L27/10855 , H01L27/10888 , H01L27/11521 , H01L29/6656
摘要： A method for fabricating a semiconductor device includes forming a recess gate over a semiconductor substrate. A gate spacer is formed on a sidewall of the recess gate. The semiconductor substrate in a landing plug contact region is soft-etched to form a recess having a rounded profile. A sidewall spacer is formed over the gate spacer and a sidewall of the recess. An insulating film is formed over the semiconductor substrate. The insulating film is selectively etched to form a landing plug contact hole. A conductive layer in the landing plug contact hole is filled to form a landing plug.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成凹陷栅极。门间隔件形成在凹槽的侧壁上。着陆塞接触区域中的半导体衬底被软蚀刻以形成具有圆形轮廓的凹部。侧壁间隔件形成在栅极间隔物和凹部的侧壁上。在半导体衬底上形成绝缘膜。绝缘膜被选择性地蚀刻以形成着陆插头接触孔。着陆塞接触孔中的导电层被填充以形成着陆塞。

3. 发明授权

US08457695B2 Mobile communication terminal having fragrance member 失效
标题翻译：具有香味构件的移动通信终端
公开(公告)号：US08457695B2
公开(公告)日：2013-06-04
申请号：US12244537
申请日：2008-10-02
申请人： Chang Youn Hwang , Young Ki Kim , Shin Chul Kang
发明人： Chang Youn Hwang , Young Ki Kim , Shin Chul Kang
IPC分类号： H04M1/00
CPC分类号： H04M1/026 , H04M1/0214 , H04M1/0235 , H04M1/0283 , H04M1/21
摘要： A mobile communication terminal includes a fixed body, and a movable body coupled with the fixed body. At least one of the fixed body and the movable body has a fragrance member at a portion thereof that generates friction when the movable body moves.
摘要翻译：移动通信终端包括固定体和与固定体联接的可移动体。固定体和移动体中的至少一个在其一部分具有香味构件，当可移动体移动时产生摩擦。

4. 发明申请

US20080160740A1 Method For Manufacturing Semiconductor Device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080160740A1
公开(公告)日：2008-07-03
申请号：US11771682
申请日：2007-06-29
申请人： Hyun Ahn , Chang Youn Hwang
发明人： Hyun Ahn , Chang Youn Hwang
IPC分类号： H01L21/3205
CPC分类号： H01L21/76897 , H01L21/76831 , H01L27/10855 , H01L27/10888
摘要： A method for manufacturing a semiconductor device comprises forming a SEG layer in a bottom of a storage node contact hole, and forming a spacer at a sidewall of a storage node contact hole and a bit line contact hole, thereby preventing expansion of the bottom of the bit line contact hole. Also, the method prevents a short phenomenon of a bit line contact plug and a recess gate, thereby improving an insulating characteristic of the device. The thickness of the spacer of the sidewall of the recess gate can be increased to protect the recess gate.
摘要翻译：一种半导体器件的制造方法，其特征在于，在存储节点接触孔的底部形成SEG层，在存储节点接触孔和位线接触孔的侧壁形成间隔物，从而防止了位线接触孔。此外，该方法防止位线接触插塞和凹槽的短暂现象，从而提高器件的绝缘特性。可以增加凹槽的侧壁的间隔件的厚度以保护凹槽。

5. 发明申请

US20080153279A1 Method For Manufacturing Semiconductor Device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080153279A1
公开(公告)日：2008-06-26
申请号：US11771811
申请日：2007-06-29
申请人： Chang Youn Hwang
发明人： Chang Youn Hwang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76831 , H01L27/10855
摘要： A method for manufacturing a semiconductor device includes the steps of: forming a primary storage node contact plug at an upper part of the exposed landing plug at a lower part of the storage node contact hole; and filling the storage node contact hole with a conductive film to form a secondary storage node contact plug. In result, the size of a storage node contact may be increase to cause the contact resistance to decrease, without any loss of the interlayer insulating film to a cleaning solution.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在存储节点接触孔的下部在暴露的着陆栓的上部形成主存储节点接触塞; 并且用导电膜填充存储节点接触孔以形成次级存储节点接触插头。结果，存储节点接触件的尺寸可能会增加，从而导致接触电阻降低，而层间绝缘膜不会损失到清洁溶液。

6. 发明申请

US20080153276A1 Method for Manufacturing Semiconductor Device 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：US20080153276A1
公开(公告)日：2008-06-26
申请号：US11771426
申请日：2007-06-29
申请人： Chang Youn Hwang , Jae Young Lee
发明人： Chang Youn Hwang , Jae Young Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/76897 , H01L21/02063 , H01L21/76814 , H01L21/76877 , H01L27/10855 , H01L27/10888
摘要： A method for manufacturing a semiconductor device is capable of increasing the size of a landing plug without loss of an insulating film separating the landing plug, and may be advantageously used for reducing contact resistance by enlarging a landing plug contact hole without causing the loss of the insulating film due to a cleaning solution during a wet cleaning process. The semiconductor device manufacturing method includes the steps of: forming a gate over a semiconductor substrate and forming an interlayer insulating film filling spaces between the gates; selectively etching the interlayer insulating film to form a landing plug contact hole; forming a primary landing plug filling the landing plug contact hole preferably by a selective epitaxial growth method; forming, over the gate, a buffer dielectric film of an over-hang structure; and forming, over the primary landing plug, a secondary landing plug as a conductive film.
摘要翻译：制造半导体器件的方法能够增加着陆塞的尺寸，而不会损坏分离着陆塞的绝缘膜，并且可以有利地用于通过扩大接地塞接触孔来减小接触电阻而不会导致在湿式清洗过程中由于清洗液而导致的绝缘膜。半导体器件制造方法包括以下步骤：在半导体衬底上形成栅极，并在栅极之间形成层间绝缘膜填充空间; 选择性地蚀刻层间绝缘膜以形成着陆塞接触孔; 优选地通过选择性外延生长方法形成填充着陆塞接触孔的主要着陆塞; 在栅极上形成悬挂结构的缓冲介电膜; 并且在主着陆塞上形成作为导电膜的次级着陆塞。

7. 发明授权

US08034714B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08034714B2
公开(公告)日：2011-10-11
申请号：US12495607
申请日：2009-06-30
申请人： Chang Youn Hwang
发明人： Chang Youn Hwang
IPC分类号： H01L29/72
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10855
摘要： Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern.
摘要翻译：提供半导体器件和制造半导体存储器件的方法。通过湿蚀刻形成接触塞。 SAC的长宽比降低，SAC故障降低，从而保证了处理余量。半导体器件包括半导体衬底，其包括有源区和限定有源区的器件隔离层，形成在半导体衬底上的导电图案，以及在半导体衬底上垂直于导电图形形成的氮化物层。

8. 发明申请

US20080150014A1 Semiconductor Device and Method for Fabricating the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080150014A1
公开(公告)日：2008-06-26
申请号：US11771478
申请日：2007-06-29
申请人： Chang Youn Hwang , Hyun Ahn
发明人： Chang Youn Hwang , Hyun Ahn
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/76897 , H01L21/3065 , H01L27/10855 , H01L27/10888 , H01L27/11521 , H01L29/6656
摘要： A method for fabricating a semiconductor device includes forming a recess gate over a semiconductor substrate. A gate spacer is formed on a sidewall of the recess gate. The semiconductor substrate in a landing plug contact region is soft-etched to form a recess having a rounded profile. A sidewall spacer is formed over the gate spacer and a sidewall of the recess. An insulating film is formed over the semiconductor substrate. The insulating film is selectively etched to form a landing plug contact hole. A conductive layer in the landing plug contact hole is filled to form a landing plug.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成凹陷栅极。门间隔件形成在凹槽的侧壁上。着陆塞接触区域中的半导体衬底被软蚀刻以形成具有圆形轮廓的凹部。侧壁间隔件形成在栅极间隔物和凹部的侧壁上。在半导体衬底上形成绝缘膜。绝缘膜被选择性地蚀刻以形成着陆插头接触孔。着陆塞接触孔中的导电层被填充以形成着陆塞。

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