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1. 发明申请

US20050024912A1 System and method for providing a redundant memory array in a semiconductor memory integrated circuit 失效
标题翻译：一种用于在半导体存储器集成电路中提供冗余存储器阵列的系统和方法
公开(公告)号：US20050024912A1
公开(公告)日：2005-02-03
申请号：US10628896
申请日：2003-07-28
申请人： Chao-Wu Chen , Richard Roy , Wasim Khaled
发明人： Chao-Wu Chen , Richard Roy , Wasim Khaled
IPC分类号： G11C11/22 , G11C29/00
CPC分类号： G11C29/846 , G11C29/842
摘要： A memory device that has an internal memory array provides timing signals to control the output timing of one or more redundant memory blocks that substitute for defective memory blocks in the internal memory array. In one embodiment, the internal memory array includes a pipelined output stage, and the timing signals ensure that the data is output from the memory devices in the order memory access requests are issued, even when the latency of the redundant memory blocks is less than the latency of the main memory array by up to two clock periods. In one embodiment, a FIFO memory queues the output data of the redundant memory blocks waiting to be output.
摘要翻译：具有内部存储器阵列的存储器件提供定时信号以控制代替内部存储器阵列中的缺陷存储器块的一个或多个冗余存储器块的输出定时。在一个实施例中，内部存储器阵列包括流水线输出级，并且定时信号确保以存储器访问请求的顺序从存储器件输出数据，即使当冗余存储器块的等待时间小于主存储器阵列延迟最多两个时钟周期。在一个实施例中，FIFO存储器对等待输出的冗余存储器块的输出数据进行排队。

2. 发明授权

US07158425B2 System and method for providing a redundant memory array in a semiconductor memory integrated circuit 失效
标题翻译：一种用于在半导体存储器集成电路中提供冗余存储器阵列的系统和方法
公开(公告)号：US07158425B2
公开(公告)日：2007-01-02
申请号：US10628896
申请日：2003-07-28
申请人： Chao-Wu Chen , Richard Roy , Wasim Khaled
发明人： Chao-Wu Chen , Richard Roy , Wasim Khaled
IPC分类号： G11C7/00
CPC分类号： G11C29/846 , G11C29/842
摘要： A memory device that has an internal memory array provides timing signals to control the output timing of one or more redundant memory blocks that substitute for defective memory blocks in the internal memory array. In one embodiment, the internal memory array includes a pipelined output stage, and the timing signals ensure that the data is output from the memory devices in the order memory access requests are issued, even when the latency of the redundant memory blocks is less than the latency of the main memory array by up to two clock periods. In one embodiment, a FIFO memory queues the output data of the redundant memory blocks waiting to be output.
摘要翻译：具有内部存储器阵列的存储器件提供定时信号以控制代替内部存储器阵列中的缺陷存储器块的一个或多个冗余存储器块的输出定时。在一个实施例中，内部存储器阵列包括流水线输出级，并且定时信号确保以存储器访问请求的顺序从存储器件输出数据，即使当冗余存储器块的等待时间小于主存储器阵列延迟最多两个时钟周期。在一个实施例中，FIFO存储器对等待输出的冗余存储器块的输出数据进行排队。

3. 发明授权

US5504903A Self-progamming of on-chip program memory for microcontroller at clock start-up 失效
标题翻译：在时钟启动时，用于微控制器的片上程序存储器的自动编程
公开(公告)号：US5504903A
公开(公告)日：1996-04-02
申请号：US192958
申请日：1994-02-07
申请人： Chao-Wu Chen , Kurt Rosenhagen , Greg Italiano , Sumit Mitra
发明人： Chao-Wu Chen , Kurt Rosenhagen , Greg Italiano , Sumit Mitra
IPC分类号： G06F9/24 , G06F9/445 , G06F9/06
CPC分类号： G06F9/24 , G06F9/445
摘要： A microcontroller fabricated on a semiconductor chip is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. A clock generates timing signals to control the timing of the microcontroller execution and operation. An on-chip program memory has space avilable for storing a program to be executed by the microcontroller in sequential steps in successive address locations of the program memory. An instruction stored in unerasable memory on the chip initiates self-programming of the program memory with the program to be executed by the microcontroller by enabling a pointer timed by the clock to alternately read addresses containing steps of the program to be executed from off-chip memories and to write same into successive addresses of the on-chip program memory by incrementing the latter addresses with each step to be written therein.
摘要翻译：制造在半导体芯片上的微控制器在操作时适于执行程序和指令，并且作为响应，适于产生控制信号以选择性地控制外部设备。时钟产生定时信号以控制微控制器执行和操作的时序。片上程序存储器具有可用于存储由微控制器在程序存储器的连续地址位置中的连续步骤执行的程序的空间。存储在芯片上的不可擦除存储器中的指令通过使由时钟指针定时的指针交替地读取包含要从芯片外执行的程序的步骤的地址，从而启动程序存储器的自编程，并由要由微控制器执行的程序存储器，并且通过用要在其中写入的每个步骤递增后一个地址，将其写入片上程序存储器的连续地址。

4. 发明申请

US20090055632A1 Emulation Scheme for Programmable Pipeline Fabric 审中-公开
标题翻译：可编程管道织物仿真方案
公开(公告)号：US20090055632A1
公开(公告)日：2009-02-26
申请号：US11843596
申请日：2007-08-22
申请人： Chao-Wu Chen
发明人： Chao-Wu Chen
IPC分类号： G06F9/30
CPC分类号： G06F11/3652 , G06F15/7867
摘要： The present invention allows emulation of a programmable pipeline processor fabric or architecture. According to certain aspects, the invention permits real-time capture of state information for any given stage of a processing flow performed by the fabric or architecture. According to other aspects, the invention allows a particular stage and data set of a SIMD flow to be analyzed. According to other aspects, the invention utilizes an independent clocking domain for the capture of state information.
摘要翻译：本发明允许仿真可编程流水线处理器结构或架构。根据某些方面，本发明允许对由结构或架构执行的处理流程的任何给定阶段的状态信息的实时捕获。根据其他方面，本发明允许分析SIMD流的特定阶段和数据集。根据其他方面，本发明利用独立的时钟域来捕获状态信息。

5. 发明授权

US06937055B2 Programmable I/O buffer 失效
标题翻译：可编程I / O缓冲器
公开(公告)号：US06937055B2
公开(公告)日：2005-08-30
申请号：US10328907
申请日：2002-12-23
申请人： Richard Stephen Roy , Ali Massoumi , Chao-Wu Chen
发明人： Richard Stephen Roy , Ali Massoumi , Chao-Wu Chen
IPC分类号： H03K19/00 , H04L25/02 , H03K19/003
CPC分类号： H04L25/0278 , H03K19/0005 , H04L25/028 , H04L25/0292
摘要： A programmable input/output buffer has a first plurality of pull-down transistors connected between a supply voltage and an electrical system conductor on the integrated circuit and a second plurality of pull-down transistors connected between the electrical conductor and the system reference voltage. Reference circuits generate signals to turn on a first number of said first plurality of pull-up transistors and/or a second number of said second plurality of pull-down transistors to provide an input/output buffer impedance matching the impedance of the external transmission line either sending a signal to the programmable input/output buffer or receiving a signal from the programmable input/output buffer.
摘要翻译：可编程输入/输出缓冲器具有连接在集成电路上的电源电压和电气系统导体之间的第一多个下拉晶体管，以及连接在电导体和系统参考电压之间的第二多个下拉晶体管。参考电路产生信号以接通第一数量的所述第一多个上拉晶体管和/或第二数量的所述第二多个下拉晶体管，以提供匹配外部传输线路的阻抗的输入/输出缓冲器阻抗将信号发送到可编程输入/输出缓冲器或从可编程输入/输出缓冲器接收信号。

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