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1. 发明申请

US20150364167A1 INTEGRATED CIRCUIT AND PRECHARGE/ACTIVE FLAG GENERATION CIRCUIT 有权
标题翻译：集成电路和预处理/主动标志生成电路
公开(公告)号：US20150364167A1
公开(公告)日：2015-12-17
申请号：US14555442
申请日：2014-11-26
申请人： SK hynix Inc.
发明人： Hyun-Sung LEE
IPC分类号： G11C7/12 , G11C8/12
CPC分类号： G11C7/12 , G11C8/12 , G11C29/787 , G11C29/842 , H03K19/20 , H03M7/165 , H03M7/24 , H03M9/00
摘要： An integrated circuit includes a first stage including first logic gates each of which performs a first logic operation on a corresponding signal among first to Nth signals and a first bit of a binary code, and a second stage including second logic gates each of which performs a second logic operation on corresponding output signals of the first logic gates and is reset based on a second bit of the binary code.
摘要翻译：集成电路包括：第一级，包括第一逻辑门，每个第一逻辑门对第一至第N信号中的对应信号和二进制码的第一位执行第一逻辑运算;第二级包括第二逻辑门，每个逻辑门执行对第一逻辑门的相应输出信号进行第二逻辑运算，并基于二进制码的第二位复位。

2. 发明授权

US09208902B2 Bitline leakage detection in memories 有权
标题翻译：存储器中的位线泄漏检测
公开(公告)号：US09208902B2
公开(公告)日：2015-12-08
申请号：US12608101
申请日：2009-10-29
申请人： Beena Pious , Xiaowei Deng , Wah Kit Loh , Jon Lescrenier
发明人： Beena Pious , Xiaowei Deng , Wah Kit Loh , Jon Lescrenier
IPC分类号： G11C29/00 , G11C29/12 , G11C29/02 , G11C11/22 , G11C11/41 , G11C29/50
CPC分类号： G11C29/842 , G11C11/22 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/12 , G11C2029/1204 , G11C2029/5006
摘要： An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.
摘要翻译：包含存储器和读出放大器的集成电路。该集成电路还包含扩展延迟电路，其扩展了预充电位线在浮动时和当字线被使能时的延迟。一种测试集成电路以识别具有过度泄漏的位线的方法。

3. 发明申请

US20110149664A1 WORD LINE BLOCK/SELECT CIRCUIT WITH REPAIR ADDRESS DECISION UNIT 有权
标题翻译：字线线路/选择电路与维修地址决定单元
公开(公告)号：US20110149664A1
公开(公告)日：2011-06-23
申请号：US13036398
申请日：2011-02-28
申请人： Seong Nyuh Yoo
发明人： Seong Nyuh Yoo
IPC分类号： G11C29/44
CPC分类号： G11C29/842
摘要： A word line block select circuit includes a dummy repair logic unit including a dummy logic circuit to output a first control signal and having a delay path for a repair address decision, and a word line activation unit for activating a word line in response to the first control signal and an active command signal.
摘要翻译：字线块选择电路包括虚拟修复逻辑单元，其包括用于输出第一控制信号并具有用于修复地址决定的延迟路径的虚拟逻辑电路，以及字线激活单元，用于响应于第一控制信号和有效指令信号。

4. 发明授权

US07782687B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07782687B2
公开(公告)日：2010-08-24
申请号：US12252974
申请日：2008-10-16
申请人： Tomohiro Kurozumi
发明人： Tomohiro Kurozumi
IPC分类号： G11C29/00
CPC分类号： G11C29/842
摘要： In a semiconductor device having a redundant memory, the area of the device is reduced and a time required to transfer relief information is reduced. Moreover, a transfer control of relief information is facilitated. A first relief information storing unit stores relief information for relieving a redundant memory having a defective cell. A plurality of redundant memories share a second relief information storing unit. The second relief information storing unit is connected in series to the first relief information storing unit. The relief information is transferred from the first relief information storing unit to the second relief information storing unit.
摘要翻译：在具有冗余存储器的半导体器件中，器件的面积减小，并且减少传递浮雕信息所需的时间。此外，促进了救济信息的转移控制。第一释放信息存储单元存储用于减轻具有缺陷单元的冗余存储器的释放信息。多个冗余存储器共享第二释放信息存储单元。第二救济信息存储单元与第一救济信息存储单元串联连接。救济信息从第一救济信息存储单元传送到第二救济信息存储单元。

5. 发明申请

US20090003118A1 Word line block select circuit with repair address decision unit 有权
标题翻译：具有修复地址决定单元的字线块选择电路
公开(公告)号：US20090003118A1
公开(公告)日：2009-01-01
申请号：US12012931
申请日：2008-02-05
申请人： Seong Nyuh Yoo
发明人： Seong Nyuh Yoo
IPC分类号： G11C8/12
CPC分类号： G11C29/842
摘要： A word line block select circuit includes a dummy repair logic unit including a dummy logic circuit to output a first control signal and having a delay path for a repair address decision, and a word line activation unit for activating a word line in response to the first control signal and an active command signal.
摘要翻译：字线块选择电路包括虚拟修复逻辑单元，其包括用于输出第一控制信号并具有用于修复地址决定的延迟路径的虚拟逻辑电路，以及字线激活单元，用于响应于第一控制信号和有效指令信号。

6. 发明授权

US07379357B2 Semiconductor memory device having advanced repair circuit 有权
标题翻译：半导体存储器件具有先进的修复电路
公开(公告)号：US07379357B2
公开(公告)日：2008-05-27
申请号：US10749836
申请日：2003-12-30
申请人： Sang-Hee Kang
发明人： Sang-Hee Kang
IPC分类号： G11C7/00
CPC分类号： G11C29/842 , G11C29/787
摘要： A semiconductor device for comparing an input address with a repair address includes a signal controller for generating control signals. An address latch unit in response to the control signals latches the address. Each of N number of M-bit address comparators compares the address with the stored repair address. A comparator delay modeling block delays the control signal for a predetermined time, i.e., delay value of the M-bit address comparator. A repair circuit controller in response to the delayed control signal output from the comparator delay modeling block generates one of a repair address enable signal and a normal address enable signal based on a comparison result of the M-bit address comparator.
摘要翻译：用于将输入地址与修复地址进行比较的半导体器件包括用于产生控制信号的信号控制器。响应于控制信号的地址锁存单元锁存地址。 N个M位地址比较器中的每一个将地址与存储的修复地址进行比较。比较器延迟建模块将控制信号延迟预定时间，即M位地址比较器的延迟值。响应于从比较器延迟建模块输出的延迟的控制信号，修复电路控制器基于M位地址比较器的比较结果产生修复地址使能信号和正常地址使能信号中的一个。

7. 发明申请

US20060140029A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060140029A1
公开(公告)日：2006-06-29
申请号：US11315698
申请日：2005-12-22
申请人： Yasushi Matsubara
发明人： Yasushi Matsubara
IPC分类号： G11C29/00
CPC分类号： G11C29/842
摘要： A redundancy replacement judging circuit includes a redundancy replacement judging circuit chain and a pseudo redundancy replacement judging circuit chain substantially equal in delay time to the redundancy replacement judging circuit chain. In response to an output of the pseudo redundancy replacement judging circuit chain, the redundancy replacement judging circuit outputs a redundancy judgment result of the redundancy replacement judging circuit chain. A semiconductor memory device includes the redundancy replacement judging circuit.
摘要翻译：冗余替换判断电路包括冗余替换判断电路链和在冗余替换判断电路链上延迟时间基本相等的伪冗余替换判断电路链。响应于伪冗余替换判断电路链的输出，冗余替换判断电路输出冗余替换判断电路链的冗余判断结果。半导体存储器件包括冗余替换判断电路。

8. 发明授权

US06982911B2 Memory device with common row interface 失效
标题翻译：具有公共行接口的内存设备
公开(公告)号：US06982911B2
公开(公告)日：2006-01-03
申请号：US10805024
申请日：2004-03-18
申请人： Jong-Hoon Oh
发明人： Jong-Hoon Oh
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/842
摘要： One embodiment of the present invention provides a semiconductor memory receiving an external address including an array address and a row address. The semiconductor memory includes a memory bank having N arrays, each array having an array address and a plurality of primary rows of memory cells and a plurality of redundant rows of memory cells, a redundancy block, and N local row control blocks. The redundancy block provides a match signal having an active state when the external address matches one of a plurality of defective addresses, provides a redundant row address when the match signal has the active state, and provides a redirected array address comprising a redundant array address when the match signal has the active state and otherwise comprising the external array address. Each of the N local row control blocks is associated with a different one of the N arrays, wherein the local row control block associated with the array whose address matches the redirected array address opens a redundant row of memory cells for access based on the redundant row address when the match signal has the first state, and otherwise opens a normal row of memory cells for access based on the external row address.
摘要翻译：本发明的一个实施例提供了接收包括阵列地址和行地址的外部地址的半导体存储器。半导体存储器包括具有N个阵列的存储体，每个阵列具有阵列地址和存储器单元的多个主行和多个存储单元冗余行，冗余块和N个本地行控制块。当外部地址匹配多个缺陷地址之一时，冗余块提供具有活动状态的匹配信号，当匹配信号具有活动状态时提供冗余行地址，并且当冗余阵列地址包括冗余阵列地址时匹配信号具有活动状态，否则包括外部阵列地址。 N个本地行控制块中的每一个与N个阵列中的不同的一个相关联，其中与地址与重定向阵列地址匹配的阵列相关联的本地行控制块基于冗余行打开用于访问的冗余行存储器单元匹配信号具有第一状态时的地址，否则基于外部行地址打开用于访问的正常的存储单元行。

9. 发明授权

US06560150B2 Memory device testing 有权
公开(公告)号：US06560150B2
公开(公告)日：2003-05-06
申请号：US10192328
申请日：2002-07-10
申请人： Ebrahim Abedifard
发明人： Ebrahim Abedifard
IPC分类号： G11C700
CPC分类号： G11C29/24 , G11C29/842
摘要： Memory devices having redundancy selection circuitry are adapted to introduce test input signals into the redundancy selection path. The memory devices include a redundancy selection circuit having a latch for latching an incoming redundancy match signal. The latch includes a pair of reverse-coupled inverters. The latch is further coupled to receive one or more test input signals. The latch is responsive to one or more control signals to selectively generate the latched match signal from the incoming redundancy match signal or one of the test input signals. Such latch circuits are useful for controlling selection of a redundant element in a memory device during testing without significantly impacting the speed path of the redundancy selection circuitry during normal operation of the memory device.

10. 发明申请

US20010035537A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20010035537A1
公开(公告)日：2001-11-01
申请号：US09839306
申请日：2001-04-23
申请人： Fujitsu Limited
发明人： Naoharu Shinozaki
IPC分类号： H01L031/0328
CPC分类号： G11C29/842 , G11C29/83 , G11C29/84
摘要： An address input circuit outputs an address signal from exterior as an internal address signal. A latching circuit accepts the internal address signal, and supplies the accepted signal to an internal circuit in conformity to the operating timing of the internal circuit. A redundancy judgement circuit judges whether or not the internal address signal yet to be accepted into the latching circuit is of a defect address, and outputs the judgement result as a redundancy judgement signal. A redundancy latching circuit accepts the redundancy judgement signal, and supplies the accepted signal to the internal circuit in conformity to the operating timing of the internal circuit. The use of the address signal before it is latched for redundancy judgement allows the redundancy judgement to be performed at earlier timing. Therefore, the amount of time needed for the read operation and write operation can be reduced.
摘要翻译：地址输入电路从外部输出地址信号作为内部地址信号。锁存电路接受内部地址信号，并根据内部电路的工作时序将接受的信号提供给内部电路。冗余判断电路判断尚未被接受到锁存电路的内部地址信号是否为缺陷地址，并将判断结果作为冗余判断信号输出。冗余锁存电路接受冗余判断信号，并根据内部电路的工作时间将接受的信号提供给内部电路。锁存用于冗余判断之前的地址信号的使用允许在较早的定时执行冗余判断。因此，可以减少读取操作和写入操作所需的时间量。

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