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1. 发明授权

US07528482B2 Embedded chip package with improved heat dissipation performance and method of making the same 有权
标题翻译：嵌入式芯片封装具有改进的散热性能和制作方法
公开(公告)号：US07528482B2
公开(公告)日：2009-05-05
申请号：US11672507
申请日：2007-02-07
申请人： Cheng-Hung Huang , Hsien-Chieh Lin , Kuo-Chun Chiang , Shing-Fun Ho
发明人： Cheng-Hung Huang , Hsien-Chieh Lin , Kuo-Chun Chiang , Shing-Fun Ho
IPC分类号： H01L23/10
CPC分类号： H01L23/5389 , H01L23/36 , H01L24/19 , H01L24/24 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/24227 , H01L2224/32245 , H01L2224/73267 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/18162 , H01L2924/3011 , H01L2924/00
摘要： A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.
摘要翻译：芯片衬底封装（CiSP）包括双面金属敷层层压板，其包括介电插入件，层叠在电介质插入件的第一侧上的第一金属箔和层叠在电介质插入件的第二侧上的第二金属箔。凹入的腔被蚀刻到第二金属箔和电介质插入件中，第一金属箔的一部分作为其底部。模具安装在凹腔内并与第一金属箔热接触。堆积材料层覆盖第二金属箔和模具的有效表面。堆积材料层还填充了管芯和电介质插入件之间的间隙。至少一个互连层设置在积层材料层上，并且通过电镀通孔与设置在管芯的有效表面上的焊盘电连接。

2. 发明申请

US20080116569A1 EMBEDDED CHIP PACKAGE WITH IMPROVED HEAT DISSIPATION PERFORMANCE AND METHOD OF MAKING THE SAME 有权
标题翻译：具有改进的散热性能的嵌入式芯片封装及其制造方法
公开(公告)号：US20080116569A1
公开(公告)日：2008-05-22
申请号：US11672507
申请日：2007-02-07
申请人： Cheng-Hung Huang , Hsien-Chieh Lin , Kuo-Chun Chiang , Shing-Fun Ho
发明人： Cheng-Hung Huang , Hsien-Chieh Lin , Kuo-Chun Chiang , Shing-Fun Ho
IPC分类号： H01L23/34
CPC分类号： H01L23/5389 , H01L23/36 , H01L24/19 , H01L24/24 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/24227 , H01L2224/32245 , H01L2224/73267 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/18162 , H01L2924/3011 , H01L2924/00
摘要： A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.
摘要翻译：芯片衬底封装（CiSP）包括双面金属敷层层压板，其包括介电插入件，层叠在电介质插入件的第一侧上的第一金属箔和层叠在电介质插入件的第二侧上的第二金属箔。凹入的腔被蚀刻到第二金属箔和电介质插入件中，第一金属箔的一部分作为其底部。模具安装在凹腔内并与第一金属箔热接触。堆积材料层覆盖第二金属箔和模具的有效表面。堆积材料层还填充了管芯和电介质插入件之间的间隙。至少一个互连层设置在积层材料层上，并且通过电镀通孔与设置在管芯的有效表面上的焊盘电连接。

3. 发明申请

US20080149732A1 LOT TRACEABLE PRINTED CIRCUIT BOARD 有权
标题翻译：可追溯打印电路板
公开(公告)号：US20080149732A1
公开(公告)日：2008-06-26
申请号：US11673596
申请日：2007-02-12
申请人： Hsing-Lun Lo , Hsien-Chieh Lin , Kuo-Chun Chiang , Shing-Fun Ho
发明人： Hsing-Lun Lo , Hsien-Chieh Lin , Kuo-Chun Chiang , Shing-Fun Ho
IPC分类号： G06K19/067
CPC分类号： H05K1/0266 , H05K1/0268 , H05K2201/09481 , H05K2201/09927
摘要： A lot traceable printed circuit board (PCB) includes a substrate having thereon a patterned circuit layer and a working zone carrying production information related to the PCB itself. The working zone includes a plurality of code boxes, wherein each of the code boxes has a first probe region and second probe region. A single set of resistance test loop is disposed within the first probe region. Four sets of resistance test loops are disposed within the second probe region. A frying probe tester is used to probe the set of resistance test loops respectively for abstracting the production information recorded in the working zone.
摘要翻译：许多可追溯的印刷电路板（PCB）包括其上具有图案化电路层的基板和承载与PCB本身相关的生产信息的工作区。工作区域包括多个代码框，其中每个代码框具有第一探测区域和第二探测区域。单个电阻测试环路设置在第一探测区域内。四组电阻测试环设置在第二探针区域内。使用油炸探针测试仪分别探测一组电阻测试回路，以抽取记录在工作区域中的生产信息。

4. 发明授权

US07576287B2 Lot traceable printed circuit board 有权
标题翻译：批量可追溯印刷电路板
公开(公告)号：US07576287B2
公开(公告)日：2009-08-18
申请号：US11673596
申请日：2007-02-12
申请人： Hsing-Lun Lo , Hsien-Chieh Lin , Kuo-Chun Chiang , Shing-Fun Ho
发明人： Hsing-Lun Lo , Hsien-Chieh Lin , Kuo-Chun Chiang , Shing-Fun Ho
IPC分类号： H05K1/00
CPC分类号： H05K1/0266 , H05K1/0268 , H05K2201/09481 , H05K2201/09927
摘要： A lot traceable printed circuit board (PCB) includes a substrate having thereon a patterned circuit layer and a working zone carrying production information related to the PCB itself. The working zone includes a plurality of code boxes, wherein each of the code boxes has a first probe region and second probe region. A single set of resistance test loop is disposed within the first probe region. Four sets of resistance test loops are disposed within the second probe region. A frying probe tester is used to probe the set of resistance test loops respectively for abstracting the production information recorded in the working zone.
摘要翻译：许多可追溯的印刷电路板（PCB）包括其上具有图案化电路层的基板和承载与PCB本身相关的生产信息的工作区。工作区域包括多个代码框，其中每个代码框具有第一探测区域和第二探测区域。单个电阻测试环路设置在第一探测区域内。四组电阻测试环设置在第二探针区域内。使用油炸探针测试仪分别探测一组电阻测试回路，以抽取记录在工作区域中的生产信息。

5. 发明申请

US20080315398A1 PACKAGING SUBSTRATE WITH EMBEDDED CHIP AND BURIED HEATSINK 审中-公开
标题翻译：包装衬底与嵌入式芯片和BURIED HEATSINK
公开(公告)号：US20080315398A1
公开(公告)日：2008-12-25
申请号：US11830822
申请日：2007-07-30
申请人： Hsing-Lun Lo , Shih-Tsung Lin , Hsien-Chieh Lin , Kuo-Chun Chiang
发明人： Hsing-Lun Lo , Shih-Tsung Lin , Hsien-Chieh Lin , Kuo-Chun Chiang
IPC分类号： H01L23/48 , H01L23/10
CPC分类号： H01L24/82 , H01L23/3675 , H01L23/3677 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L2224/12105 , H01L2224/24227 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H05K1/0206 , H05K1/183 , H05K1/185 , H05K3/4644 , H05K2201/09981 , H05K2201/10674 , H01L2924/00 , H01L2224/0401
摘要： An embedded chip package includes a substrate having a dielectric interposer, a first metal foil on a first surface and a second metal foil on a second surface of the substrate, wherein the substrate has a cavity recessed into the first surface; a metal heatsink embedded within the cavity; a semiconductor die mounted on a flat bottom of the metal heatsink; a dielectric layer covering the first surface of the substrate; at least one built-up circuit trace layer on the dielectric layer; a solder resist layer on the built-up circuit trace layer and on the dielectric layer; a heat-dissipating metal layer on the second metal foil; and heat-dissipating plugs connecting the flat bottom of the metal heatsink and the heat-dissipating metal layer.
摘要翻译：嵌入式芯片封装包括具有电介质插入件的基板，在第一表面上的第一金属箔和在基板的第二表面上的第二金属箔，其中所述基板具有凹入所述第一表面的空腔; 嵌入腔内的金属散热器; 安装在金属散热器的平坦底部的半导体管芯; 覆盖基板的第一表面的电介质层; 电介质层上的至少一个积聚电路迹线层; 在积层电路迹线层和电介质层上的阻焊层; 第二金属箔上的散热金属层; 以及连接金属散热器的平坦底部和散热金属层的散热塞。

6. 发明申请

US20110036620A1 PRINTED CIRCUIT BOARD AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：印刷电路板及其制造方法
公开(公告)号：US20110036620A1
公开(公告)日：2011-02-17
申请号：US12563975
申请日：2009-09-21
申请人： Hsien-Chieh Lin
发明人： Hsien-Chieh Lin
IPC分类号： H05K1/11 , B23K1/20
CPC分类号： H05K3/3457 , H05K1/116 , H05K3/3452 , H05K3/4092 , H05K3/4644 , H05K2201/0397 , H05K2201/092 , H05K2201/09436 , H05K2201/09781 , H05K2203/043
摘要： The invention provides a printed circuit board and method for fabricating the same. The printed circuit board includes a substrate having an internal circuit structure. An additional circuit structure is disposed on the substrate, electrically connected to the internal circuit structure. A solder mask insulating layer having an opening is disposed on the additional circuit structure. A conductive bump pattern is disposed in the solder mask insulating layer, wherein the conductive bump pattern extends into the opening horizontally, wherein a side, a portion of an upper surface and a portion of a lower surface of the conductive bump pattern are exposed from the opening from the opening. A solder ball is formed in the opening, wherein the solder ball is electrically connected to the additional circuit structure.
摘要翻译：本发明提供一种印刷电路板及其制造方法。印刷电路板包括具有内部电路结构的基板。附加的电路结构设置在基板上，电连接到内部电路结构。具有开口的焊接掩模绝缘层设置在附加电路结构上。导电凸块图案设置在焊料掩模绝缘层中，其中导电凸块图案水平地延伸到开口中，其中导电凸块图案的一侧，上表面的一部分和下表面的一部分从从开幕开幕。在开口中形成焊球，其中焊球与附加电路结构电连接。

7. 发明授权

US08378225B2 Printed circuit board and method for fabricating the same 有权
标题翻译：印刷电路板及其制造方法
公开(公告)号：US08378225B2
公开(公告)日：2013-02-19
申请号：US12563975
申请日：2009-09-21
申请人： Hsien-Chieh Lin
发明人： Hsien-Chieh Lin
IPC分类号： H05K1/03
CPC分类号： H05K3/3457 , H05K1/116 , H05K3/3452 , H05K3/4092 , H05K3/4644 , H05K2201/0397 , H05K2201/092 , H05K2201/09436 , H05K2201/09781 , H05K2203/043
摘要： The invention provides a printed circuit board and method for fabricating the same. The printed circuit board includes a substrate having an internal circuit structure. An additional circuit structure is disposed on the substrate, electrically connected to the internal circuit structure. A solder mask insulating layer having an opening is disposed on the additional circuit structure. A conductive bump pattern is disposed in the solder mask insulating layer, wherein the conductive bump pattern extends into the opening horizontally, wherein a side, a portion of an upper surface and a portion of a lower surface of the conductive bump pattern are exposed from the opening. A solder ball is formed in the opening, wherein the solder ball is electrically connected to the additional circuit structure.
摘要翻译：本发明提供一种印刷电路板及其制造方法。印刷电路板包括具有内部电路结构的基板。附加的电路结构设置在基板上，电连接到内部电路结构。具有开口的焊接掩模绝缘层设置在附加电路结构上。导电凸块图案设置在焊料掩模绝缘层中，其中导电凸块图案水平地延伸到开口中，其中导电凸块图案的一侧，上表面的一部分和下表面的一部分从开放在开口中形成焊球，其中焊球与附加电路结构电连接。

8. 发明授权

US08420954B2 Printed circuit board and method for fabricating the same 有权
标题翻译：印刷电路板及其制造方法
公开(公告)号：US08420954B2
公开(公告)日：2013-04-16
申请号：US12956724
申请日：2010-11-30
申请人： Hsien-Chieh Lin , Tung-Yu Chang
发明人： Hsien-Chieh Lin , Tung-Yu Chang
IPC分类号： H05K1/11
CPC分类号： H05K1/0203 , H01L23/473 , H01L23/49822 , H01L23/5389 , H01L24/19 , H01L2224/04105 , H01L2224/73267 , H01L2924/15153 , H05K1/0272 , H05K1/185 , H05K3/4602 , H05K2201/09845 , H05K2201/09854 , H05K2203/1469 , Y10T29/49155 , Y10T29/49156
摘要： The invention provides a printed circuit board and a method for fabricating the same. The printed circuit board includes a core substrate having a first surface and an opposite second surface. A first through hole and a second through hole are formed through a portion of the core substrate, respectively from the first surface and second surfaces, wherein the first and second through holes are laminated vertically and connect to each other. A first guide rail and a second guide rail are, respectively, formed through a portion of the core substrate and connected to the second through hole, so that a fluid flows sequentially from an outside of the printed circuit board through the first guide rail, the second through hole and the second guide rail, to the outside of the printed circuit board.
摘要翻译：本发明提供一种印刷电路板及其制造方法。印刷电路板包括具有第一表面和相对的第二表面的芯基板。分别从第一表面和第二表面穿过芯基板的一部分形成第一通孔和第二通孔，其中第一和第二通孔垂直地层叠并且彼此连接。第一导轨和第二导轨分别通过芯基板的一部分形成并连接到第二通孔，使得流体从印刷电路板的外部依次流过第一导轨，第二通孔和第二导轨，连接到印刷电路板的外部。

9. 发明申请

US20110220403A1 SIDE PACKAGED TYPE PRINTED CIRCUIT BOARD 审中-公开
标题翻译：侧面包装印刷电路板
公开(公告)号：US20110220403A1
公开(公告)日：2011-09-15
申请号：US12762093
申请日：2010-04-16
申请人： Hsien-Chieh Lin
发明人： Hsien-Chieh Lin
IPC分类号： H05K1/11
CPC分类号： H05K3/403 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H05K3/0052 , H05K3/3405 , H05K3/4602 , H05K2201/0919 , H05K2201/10446 , H01L2924/00
摘要： The invention provides a side packaged type printed circuit board. The side packaged type printed circuit board includes a circuit substrate having a surface and an adjacent side surface. An inner circuit covers a portion of the surface. A first side electrical connecting pad electrically connects to the inner circuit, wherein the first side electrical connecting pad and the inner circuit are in the same additional layer.
摘要翻译：本发明提供一种侧面封装型印刷电路板。侧面封装型印刷电路板包括具有表面和相邻侧表面的电路基板。内部电路覆盖表面的一部分。第一侧电连接垫电连接到内部电路，其中第一侧电连接焊盘和内部电路处于相同的附加层中。

10. 发明申请

US20110100695A1 PRINTED CIRCUIT BOARD STRUCTURE 有权
标题翻译：印刷电路板结构
公开(公告)号：US20110100695A1
公开(公告)日：2011-05-05
申请号：US12646904
申请日：2009-12-23
申请人： Hsien-Chieh Lin
发明人： Hsien-Chieh Lin
IPC分类号： H05K1/11
CPC分类号： H05K1/111 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H05K1/113 , H05K3/243 , H05K3/3452 , H05K3/3457 , H05K3/4644 , H05K2201/09745 , H05K2201/099 , Y02P70/611 , H01L2924/00
摘要： Disclosed is a printed circuit board structure which is manufactured by providing a core board, forming an inner circuit layer on the core board surface, forming a bonding pad on the inner circuit, forming a ring-shaped anti-etching layer on the bonding pad, forming an anti-soldering insulation layer on the ring-shaped anti-etching layer and the bonding pad, and forming an opening to expose a part of the bonding pad, wherein the radius of the opening is shorter than the radius of the ring-shaped anti-etching layer, and the bonding pad surface is free of concave. The described structure may prevent the solder extending along the bottom void of the anti-soldering insulation layer to other regions.
摘要翻译：公开了一种印刷电路板结构，其通过提供芯板来制造，在芯板表面上形成内部电路层，在内部电路上形成接合焊盘，在接合焊盘上形成环状抗蚀刻层，在所述环形防蚀层和所述接合焊盘上形成防焊绝缘层，并且形成用于暴露所述接合焊盘的一部分的开口，其中所述开口的半径比所述环形防蚀层的半径小抗蚀刻层，并且焊盘表面没有凹陷。所描述的结构可以防止焊料沿着防焊绝缘层的底部空隙延伸到其它区域。

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