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1. 发明授权

US06233706B1 Method and apparatus for limited access circuit test 失效
标题翻译：有限接入电路测试方法和装置
公开(公告)号：US06233706B1
公开(公告)日：2001-05-15
申请号：US09169320
申请日：1998-10-09
申请人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , John E. McDermid , Kay C . Lannen
发明人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , John E. McDermid , Kay C . Lannen
IPC分类号： G01R3128
CPC分类号： G01R31/2801 , G01R31/2846
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

2. 发明授权

US06266787B1 Method and apparatus for selecting stimulus locations during limited access circuit test 失效
标题翻译：用于在受限访问电路测试期间选择刺激位置的方法和装置
公开(公告)号：US06266787B1
公开(公告)日：2001-07-24
申请号：US09169597
申请日：1998-10-09
申请人： John E. McDermid , Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , Kay C. Lannen
发明人： John E. McDermid , Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , Kay C. Lannen
IPC分类号： G05B19048
CPC分类号： G01R31/27
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

3. 发明授权

US06263476B1 Method and apparatus for selecting targeted components in limited access test 失效
标题翻译：用于在有限访问测试中选择目标组件的方法和装置
公开(公告)号：US06263476B1
公开(公告)日：2001-07-17
申请号：US09169777
申请日：1998-10-09
申请人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid , Kay C. Lannen
发明人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid , Kay C. Lannen
IPC分类号： G06F1750
CPC分类号： G01R31/27
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

4. 发明授权

US06237118B1 Method and apparatus for correcting for detector inaccuracies in limited access testing 失效
标题翻译：用于在受限访问测试中校正检测器不准确度的方法和装置
公开(公告)号：US06237118B1
公开(公告)日：2001-05-22
申请号：US09169709
申请日：1998-10-09
申请人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , John E. McDermid
发明人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , John E. McDermid
IPC分类号： G01R3128
CPC分类号： G01R31/2806
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

5. 发明授权

US06467051B1 Method and apparatus for selecting test point nodes of a group of components having both accessible and inaccessible nodes for limited access circuit test 失效
标题翻译：用于选择具有可访问和不可访问节点的一组组件的测试点节点用于受限访问电路测试的方法和装置
公开(公告)号：US06467051B1
公开(公告)日：2002-10-15
申请号：US09169421
申请日：1998-10-09
申请人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid , Kay C. Lannen
发明人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid , Kay C. Lannen
IPC分类号： G06F1338
CPC分类号： G01R31/318502
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

6. 发明授权

US06334100B1 Method and apparatus for electronic circuit model correction 失效
标题翻译：电子电路模型校正的方法和装置
公开(公告)号：US06334100B1
公开(公告)日：2001-12-25
申请号：US09169502
申请日：1998-10-09
申请人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , Kay C. Lannen , John E. McDermid , Jamie P. Romero
发明人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , Kay C. Lannen , John E. McDermid , Jamie P. Romero
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G01R31/2837
摘要： A method for evaluating and correcting a model of an electronic circuit. A list is created which comprises the minimum number of components that must be specified by the operator in order to be able to compute values for the remaining circuit components. Correction of circuit models can be performed even in cases of limited accessibility to the circuit's nodes.
摘要翻译：一种用于评估和校正电子电路模型的方法。创建列表，其包括操作者必须指定的最小数量的组件，以便能够计算剩余电路组件的值。即使在对电路节点的可访问性有限的情况下也可以进行电路模型的校正。

7. 发明授权

US06327545B1 Method and apparatus for board model correction 失效
标题翻译：在电路测试期间消除由测量系统引起的误差的方法和装置
公开(公告)号：US06327545B1
公开(公告)日：2001-12-04
申请号：US09169710
申请日：1998-10-09
申请人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid
发明人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid
IPC分类号： G01R3500
CPC分类号： G01R31/2801 , G01R31/2846
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

8. 发明授权

US6097203A Integrated or intrapackage capability for testing electrical continuity between an integrated circuit and other circuitry 失效
公开(公告)号：US6097203A
公开(公告)日：2000-08-01
申请号：US73474
申请日：1998-05-06
申请人： Kenneth P. Parker , John E. McDermid
发明人： Kenneth P. Parker , John E. McDermid
IPC分类号： G01R31/26 , G01R31/28 , G01R31/312 , H01L21/60 , G01R31/04
CPC分类号： G01R31/312 , G01R31/2884 , H01L2224/05001 , H01L2224/05022 , H01L2224/05184 , H01L2224/05568 , H01L2224/056 , H01L2224/1134 , H01L2224/13144 , H01L2224/16 , H01L2224/45144 , H01L2224/48091 , H01L2224/48245 , H01L2224/48247 , H01L2924/00013 , H01L2924/01019 , H01L2924/01079 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025
摘要： An electromagnetic probe is integrated within an integrated circuit or mounted within an IC package to provide a capability for testing continuity between the integrated circuit and a substrate to which the integrated circuit is mounted. In a first embodiment, capacitive test probes are integrated within the integrated circuit, underneath bonding pads. In a second embodiment, Hall-effect devices are integrated within the integrated circuit underneath bonding pads. In a third embodiment, an inductive loop is integrated within the integrated circuit underneath bonding pads. In a fourth embodiment, an IC package assembly includes an internal capacitive test probe for electrical continuity testing. An internal shield may also be used as a capacitive test probe. In a fifth embodiment, an IC package assembly includes an inductive loop within the package for electrical continuity testing. The integrated or intrapackage test probes provide electromagnetic coupling to bonding pads or to a lead frame and to bonding wires (if present), to detect whether there is electrical continuity between an integrated circuit bonding pad or lead frame and conductors on an external substrate. The integrated or intrapackage test probes enable continuity testing for direct-bonding with no package, or for a package assembly even if the package assembly includes grounded shielding or a grounded heat sink.

9. 发明授权

US5274336A Capacitively-coupled test probe 失效
标题翻译：电容耦合测试探头
公开(公告)号：US5274336A
公开(公告)日：1993-12-28
申请号：US820711
申请日：1992-01-14
申请人： David T. Crook , John M. Heumann , John E. McDermid , Ronald J. Peiffer , Ed O. Schlotzhauer
发明人： David T. Crook , John M. Heumann , John E. McDermid , Ronald J. Peiffer , Ed O. Schlotzhauer
IPC分类号： G01R1/06 , F02P17/00 , G01R1/067 , G01R1/07 , G01R31/26 , G01R31/28 , G01R31/302 , G01R31/312 , G01R27/26
CPC分类号： G01R31/2806 , G01R1/07 , G01R31/2886 , G01R31/312 , F02P2017/006 , G01R31/3025
摘要： The invention is a capacitively coupled probe which can be used for non-contact acquisition of both analog and digital signals. The probe includes a shielded probe tip, a probe body which is mechanically coupled to the probe tip, and an amplifier circuit disposed within the probe body. The amplifier circuit receives a capacitively sensed signal from the probe tip and produces an amplified signal in response thereto. The amplifier has a large bandwidth to accommodate high-frequency digital signals. Further, the amplifier has a very low input capacitance and a high input resistance to reduce signal attenuation and loading of the circuit being probed. The amplifier circuit is disposed in the probe body closely adjacent to the probe tip in order to reduce stray and distributed capacitances. A reconstruction circuit reconstructs digital signals from the amplified capacitively sensed signal.

10. 发明授权

US6087842A Integrated or intrapackage capability for testing electrical continuity between an integrated circuit and other circuitry 失效
标题翻译：用于测试集成电路和其他电路之间电气连续性的集成或内部封装能力
公开(公告)号：US6087842A
公开(公告)日：2000-07-11
申请号：US639580
申请日：1996-04-29
申请人： Kenneth P. Parker , John E. McDermid
发明人： Kenneth P. Parker , John E. McDermid
IPC分类号： G01R31/26 , G01R31/28 , G01R31/312 , H01L21/60 , G01R31/04
CPC分类号： G01R31/312 , G01R31/2884 , H01L2224/05001 , H01L2224/05022 , H01L2224/05184 , H01L2224/05568 , H01L2224/056 , H01L2224/1134 , H01L2224/13144 , H01L2224/16 , H01L2224/45144 , H01L2224/48091 , H01L2224/48245 , H01L2224/48247 , H01L2924/00013 , H01L2924/01019 , H01L2924/01079 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025
摘要： An electromagnetic probe is integrated within an integrated circuit or mounted within an IC package to provide a capability for testing continuity between the integrated circuit and a substrate to which the integrated circuit is mounted. In a first embodiment, capacitive test probes are integrated within the integrated circuit, underneath bonding pads. In a second embodiment, Hall-effect devices are integrated within the integrated circuit underneath bonding pads. In a third embodiment, an inductive loop is integrated within the integrated circuit underneath bonding pads. In a fourth embodiment, an IC package assembly includes an internal capacitive test probe for electrical continuity testing. An internal shield may also be used as a capacitive test probe. In a fifth embodiment, an IC package assembly includes an inductive loop within the package for electrical continuity testing. The integrated or intrapackage test probes provide electromagnetic coupling to bonding pads or to a lead frame and to bonding wires (if present), to detect whether there is electrical continuity between an integrated circuit bonding pad or lead frame and conductors on an external substrate. The integrated or intrapackage test probes enable continuity testing for direct-bonding with no package, or for a package assembly even if the package assembly includes grounded shielding or a grounded heat sink.
摘要翻译：电磁探头集成在集成电路内或安装在IC封装内，以提供测试集成电路与集成电路所安装的基板之间的连续性的能力。在第一实施例中，电容测试探针集成在集成电路内，在焊盘下方。在第二实施例中，霍尔效应器件集成在焊盘下方的集成电路内。在第三实施例中，感应回路集成在焊盘下方的集成电路内。在第四实施例中，IC封装组件包括用于电连续性测试的内部电容测试探针。内部屏蔽也可用作电容测试探头。在第五实施例中，IC封装组件包括用于电连续性测试的封装内的感应回路。集成或内部封装测试探针提供电磁耦合到接合焊盘或引线框架和接合线（如果存在），以检测集成电路焊盘或引线框架与外部衬底上的导体之间是否存在电连续性。集成或内部封装测试探针能够进行连续测试，无需封装即可直接连接，也可用于封装组件，即使封装组件包括接地屏蔽或接地散热器。

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