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1. 发明授权

US06233706B1 Method and apparatus for limited access circuit test 失效
标题翻译：有限接入电路测试方法和装置
公开(公告)号：US06233706B1
公开(公告)日：2001-05-15
申请号：US09169320
申请日：1998-10-09
申请人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , John E. McDermid , Kay C . Lannen
发明人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , John E. McDermid , Kay C . Lannen
IPC分类号： G01R3128
CPC分类号： G01R31/2801 , G01R31/2846
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

2. 发明授权

US06266787B1 Method and apparatus for selecting stimulus locations during limited access circuit test 失效
标题翻译：用于在受限访问电路测试期间选择刺激位置的方法和装置
公开(公告)号：US06266787B1
公开(公告)日：2001-07-24
申请号：US09169597
申请日：1998-10-09
申请人： John E. McDermid , Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , Kay C. Lannen
发明人： John E. McDermid , Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , Kay C. Lannen
IPC分类号： G05B19048
CPC分类号： G01R31/27
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

3. 发明授权

US06263476B1 Method and apparatus for selecting targeted components in limited access test 失效
标题翻译：用于在有限访问测试中选择目标组件的方法和装置
公开(公告)号：US06263476B1
公开(公告)日：2001-07-17
申请号：US09169777
申请日：1998-10-09
申请人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid , Kay C. Lannen
发明人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid , Kay C. Lannen
IPC分类号： G06F1750
CPC分类号： G01R31/27
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

4. 发明授权

US06237118B1 Method and apparatus for correcting for detector inaccuracies in limited access testing 失效
标题翻译：用于在受限访问测试中校正检测器不准确度的方法和装置
公开(公告)号：US06237118B1
公开(公告)日：2001-05-22
申请号：US09169709
申请日：1998-10-09
申请人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , John E. McDermid
发明人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , John E. McDermid
IPC分类号： G01R3128
CPC分类号： G01R31/2806
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

5. 发明授权

US06467051B1 Method and apparatus for selecting test point nodes of a group of components having both accessible and inaccessible nodes for limited access circuit test 失效
标题翻译：用于选择具有可访问和不可访问节点的一组组件的测试点节点用于受限访问电路测试的方法和装置
公开(公告)号：US06467051B1
公开(公告)日：2002-10-15
申请号：US09169421
申请日：1998-10-09
申请人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid , Kay C. Lannen
发明人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid , Kay C. Lannen
IPC分类号： G06F1338
CPC分类号： G01R31/318502
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

6. 发明授权

US06334100B1 Method and apparatus for electronic circuit model correction 失效
标题翻译：电子电路模型校正的方法和装置
公开(公告)号：US06334100B1
公开(公告)日：2001-12-25
申请号：US09169502
申请日：1998-10-09
申请人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , Kay C. Lannen , John E. McDermid , Jamie P. Romero
发明人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , Kay C. Lannen , John E. McDermid , Jamie P. Romero
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G01R31/2837
摘要： A method for evaluating and correcting a model of an electronic circuit. A list is created which comprises the minimum number of components that must be specified by the operator in order to be able to compute values for the remaining circuit components. Correction of circuit models can be performed even in cases of limited accessibility to the circuit's nodes.
摘要翻译：一种用于评估和校正电子电路模型的方法。创建列表，其包括操作者必须指定的最小数量的组件，以便能够计算剩余电路组件的值。即使在对电路节点的可访问性有限的情况下也可以进行电路模型的校正。

7. 发明授权

US06327545B1 Method and apparatus for board model correction 失效
标题翻译：在电路测试期间消除由测量系统引起的误差的方法和装置
公开(公告)号：US06327545B1
公开(公告)日：2001-12-04
申请号：US09169710
申请日：1998-10-09
申请人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid
发明人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid
IPC分类号： G01R3500
CPC分类号： G01R31/2801 , G01R31/2846
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

8. 发明授权

US06667628B2 Method and apparatus for the management of forces in a wireless fixture 失效
标题翻译：用于管理无线固定装置中的力的方法和装置
公开(公告)号：US06667628B2
公开(公告)日：2003-12-23
申请号：US10114546
申请日：2002-04-02
申请人： Cherif Ahrikencheikh , Julie L Stahmer
发明人： Cherif Ahrikencheikh , Julie L Stahmer
IPC分类号： G01R3102
CPC分类号： G01R31/2808
摘要： The present invention is directed to a method and apparatus for balancing forces in a fixture and reducing forces in a probe plate (208) housed in the fixture. A plurality of double-ended probes (200) are positioned in the probe plate (208). A first bit (216), located at one of the double-ended probe (200) is in contact with a board under test (206). A second bit (218), which is oppositely disposed and located on the other end of the double-ended probe (200) is in contact with a wireless PCB (202). A spring (220) runs the length of the double-ended probe (200) and is in contact with the first bit (216) and the second bit (218).
摘要翻译：本发明涉及一种用于平衡固定装置中的力和减少容纳在固定装置中的探针板（208）中的力的方法和装置。多个双端探针（200）定位在探针板（208）中。位于双端探针（200）中的一个的第一位（216）与被测试板（206）接触。相对设置并位于双端探头（200）的另一端的第二位（218）与无线PCB（202）接触。弹簧（220）延伸双端探头（200）的长度并与第一位（216）和第二位（218）接触。

9. 发明申请

US20050093552A1 Determining points of maximum deflection of a printed circuit board under test 失效
标题翻译：确定被测印刷电路板的最大偏转点
公开(公告)号：US20050093552A1
公开(公告)日：2005-05-05
申请号：US10983923
申请日：2004-11-08
申请人： Cherif Ahrikencheikh
发明人： Cherif Ahrikencheikh
IPC分类号： G06F17/50 , G01R31/00
CPC分类号： G06F17/5072
摘要： A system and method for determining locations of maximum deflection of a printed circuit board (PCB) under test conditioned by boundary and loading conditions of the PCB, first vertical force magnitudes at associated first vertical force locations to be applied to the PCB by a tester fixture in a first direction, and second vertical force magnitudes at associated second vertical force locations to be applied to the PCB by the tester fixture in a second direction. Fixture components may be added to the design to the fixture design and the method iteratively executed until the magnitude of the maximum deflection is less than or equal to a predetermined maximum deflection magnitude.
摘要翻译：用于确定由PCB的边界和负载条件调节的受测试的印刷电路板（PCB）的最大偏转位置的系统和方法，用于通过测试夹具施加到PCB的相关联的第一垂直力位置处的第一垂直力量并且在相关联的第二垂直力位置处的第二垂直力量值由测试器夹具沿第二方向施加到PCB。夹具组件可以被添加到设计中，使得夹具设计和迭代执行的方法直到最大偏转的幅度小于或等于预定的最大偏转幅度。

10. 发明授权

US06873147B2 Optimized pin assignment with constraints 失效
标题翻译：优化引脚分配约束
公开(公告)号：US06873147B2
公开(公告)日：2005-03-29
申请号：US10602339
申请日：2003-06-24
申请人： Cherif Ahrikencheikh
发明人： Cherif Ahrikencheikh
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2801 , G01R31/2834 , G01R31/2836
摘要： A novel method for finding optimized solutions for assigning pins to probes in a constrained tester environment is presented. Given a test system network, including the nodes, probes, pins, resources, probe-to-resource mappings, resource-to-pin mappings, and test-to-resource mappings, and constraints including a Multiple-Resource-Per-Probe Constraint, a Same-Module Constraint, and/or a Multiplexing Constraint, the test system network is modeled as a Network Flow Problem to handle all of the constraints of the constrained pin-to-probe assignment problem, using “dummy” probes where necessary to model the constrained network. A modified Maximum Flow Algorithm that satisfies the network constraints is applied to the Network Flow Problem to generate a solution to said constrained pin-to-probe assignment problem.
摘要翻译：提出了一种用于在受限测试环境中为探针分配引脚的优化解决方案。给定一个测试系统网络，包括节点，探针，引脚，资源，探针到资源映射，资源对引脚映射以及测试到资源映射以及约束，包括多资源探测器约束，相同模块约束和/或多路复用约束，测试系统网络被建模为网络流问题，以处理受限的引脚到探针分配问题的所有约束，在必要时使用“虚拟”探针模拟受限网络。满足网络约束的修改的最大流量算法被应用于网络流问题以产生对所述约束的针对探针分配问题的解决方案。

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