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1. 发明授权

US08188798B1 Programmable electro-magnetic-interference (EMI) reduction with enhanced noise immunity and process tolerance 有权
标题翻译：可编程电磁干扰（EMI）降低，增强抗噪声和工艺容差
公开(公告)号：US08188798B1
公开(公告)日：2012-05-29
申请号：US12948896
申请日：2010-11-18
申请人： Chi Tak (Gerry) Leung , Chik Wai (David) Ng , Hing Kit Kwan , Wai Kit (Victor) So , Po Wah (Patrick) Chang , Wing Cheong Mak , Kwok Kuen (David) Kwong
发明人： Chi Tak (Gerry) Leung , Chik Wai (David) Ng , Hing Kit Kwan , Wai Kit (Victor) So , Po Wah (Patrick) Chang , Wing Cheong Mak , Kwok Kuen (David) Kwong
IPC分类号： H03B29/00 , H03K3/26
CPC分类号： H03L7/08
摘要： A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC.
摘要翻译：频率抖动电路通过扩展时钟的频谱来减少引起电磁干扰（EMI）的辐射。该时钟是将数字计数值驱动到数模转换器（DAC）的计数器。 DAC输出宽电压摆幅的锯齿波。减法器缩小电压摆幅，产生用作上限电压的减小摆动锯齿波。当电流泵对电容器充电和放电超过电压限制时，比较器触发设置复位锁存器来切换时钟。由于上限电压是来自减法器的减少的锯齿波，所以对电容器充电的时间量变化，使时钟的周期抖动。可以通过对减法器中的反馈电阻进行编程来调整抖动度。减法器可降低抖动对DAC误差的灵敏度，从而实现廉价，精度更低的DAC。

2. 发明授权

US08300431B2 Constant-current control module using inverter filter multiplier for off-line current-mode primary-side sense isolated flyback converter 有权
标题翻译：恒流控制模块采用变频器滤波器，用于离线电流模式初级侧感测隔离反激式转换器
公开(公告)号：US08300431B2
公开(公告)日：2012-10-30
申请号：US12718707
申请日：2010-03-05
申请人： Chik Wai (David) Ng , Hing Kit Kwan , Po Wah (Patrick) Chang , Wai Kit (Victor) So , Kwok Kuen (David) Kwong
发明人： Chik Wai (David) Ng , Hing Kit Kwan , Po Wah (Patrick) Chang , Wai Kit (Victor) So , Kwok Kuen (David) Kwong
IPC分类号： H02M3/335
CPC分类号： H02M3/335
摘要： A fly-back AC-DC power converter has a constant-current control loop that senses the primary output current in a transformer to control the secondary output without an expensive opto-isolator. A primary-side control circuit can use either a Quasi-Resonant (QR) or a Pulse-Width-Modulation (PWM) control loop to switch primary current through the transformer on and off. A feedback voltage is compared to a primary-side voltage sensed from the primary current loop to turn the switch on and off. A multiplier loop generates the feedback voltage using a multiplier. A level-shift inverter and a low-pass filter act as the multiplier by multiplying an off duty cycle of the switch by the feedback voltage to generate a filtered voltage. A high-gain error amp compares the filtered voltage to a reference voltage to generate the feedback voltage. The multiplier produces a simple relationship between the secondary current and the reference voltage, yielding simplified current control.
摘要翻译：回扫AC-DC电力转换器具有恒定电流控制回路，其感测变压器中的主要输出电流，以在没有昂贵的光隔离器的情况下控制次级输出。初级侧控制电路可以使用准谐振（QR）或脉冲宽度调制（PWM）控制回路来切换通过变压器的一次电流的开和关。将反馈电压与从初级电流回路感测的初级侧电压进行比较，以打开和关闭开关。乘法器环路使用乘法器产生反馈电压。电平移位反相器和低通滤波器通过将开关的占空比乘以反馈电压作为乘法器，以产生滤波电压。高增益误差放大器将滤波电压与参考电压进行比较，以产生反馈电压。乘法器产生二次电流和参考电压之间的简单关系，产生简化的电流控制。

3. 发明申请

US20100164625A1 Slew-Rate-Enhanced Error Amp with Adaptive Transconductance and Single Dominant Pole Shared by Main and Auxiliary Amps 有权
标题翻译：具有自适应跨导和主主导极共同的主要和辅助放大器的转换率增益误差放大器
公开(公告)号：US20100164625A1
公开(公告)日：2010-07-01
申请号：US12345862
申请日：2008-12-30
申请人： Yat To (William) Wong , Chik Wai (David) Ng , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
发明人： Yat To (William) Wong , Chik Wai (David) Ng , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F3/3023 , H03F3/45475 , H03F2203/45248 , H03F2203/45646 , H03F2203/45652 , H03F2203/45678
摘要： An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers.
摘要翻译：误差放大器可用于控制功率调节晶体管。误差放大器具有主放大器，上拉辅助放大器和全部驱动输出的下拉辅助放大器。输出上的补偿电容为所有放大器设置单个主极，从而提高稳定性。当差分输入具有大于有意偏移的绝对电压差时，来自辅助放大器的增加的转换电流提供高转换速率。通过调整辅助放大器的一个支路中的p沟道至n沟道晶体管比，将有意的偏移引入辅助放大器。主放大器中的源极退化电阻通过连接接收差分输入的两个差分晶体管的源极减小了供电余量并增加了线性度。串联晶体管增加了增益和输出阻抗。在放大器中没有使用正反馈的情况下，可靠性提高。

4. 发明授权

US08258864B1 Ultra low voltage multi-stage high-speed CMOS comparator with autozeroing 有权
标题翻译：具有自动调零功能的超低压多级高速CMOS比较器
公开(公告)号：US08258864B1
公开(公告)日：2012-09-04
申请号：US13238236
申请日：2011-09-21
申请人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
发明人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
IPC分类号： H03F1/02
CPC分类号： H03F3/45183 , H03F3/45636 , H03F2200/261 , H03F2200/294 , H03F2200/453 , H03F2203/45616 , H03F2203/45628
摘要： A pre-amplifier circuit can be cascaded and drive a latch for use in a precision analog-to-digital converter (ADC). The pre-amplifier has a main section and a feedback section connected by feedback resistors that do not produce voltage drops in the main section. Offset is stored on offset capacitors during an autozeroing phase and isolated by transmission gates during an amplifying phase. The offset capacitors drive the gates of feedback transistors that drive output nodes in the main section. Autozeroing sink transistors in the feedback section operate in the linear region while current sink transistors in the main section operate in the saturated region. Kickback-charge isolation transistors may be added for charge isolation. The output may also be equalized by an equalizing transmission gate. A very low power-supply voltage is supported even for high-speed operation with offset cancellation, due to the folded feedback resistor arrangement.
摘要翻译：前级放大器电路可以级联并驱动锁存器，用于精密模数转换器（ADC）。前置放大器有一个主要部分和一个反馈部分，通过反馈电阻连接，主部分不产生电压降。偏移量在自动调零阶段存储在偏移电容上，并在放大阶段由传输门隔离。偏移电容器驱动驱动主部分中的输出节点的反馈晶体管的栅极。反馈部分中的自动归零陷波晶体管工作在线性区域，而主部分中的电流吸收晶体管工作在饱和区域。可以添加Kickback电荷隔离晶体管用于电荷隔离。输出也可以通过均衡的传输门来均衡。由于折叠的反馈电阻器布置，即使对于具有偏移消除的高速操作也支持非常低的电源电压。

5. 发明授权

US08643988B1 ESD power clamp using a low-voltage transistor to clamp a high-voltage supply in a mixed-voltage chip 有权
标题翻译：使用低压晶体管的ESD功率钳位钳位混合电压芯片中的高压电源
公开(公告)号：US08643988B1
公开(公告)日：2014-02-04
申请号：US13625986
申请日：2012-09-25
申请人： Kwok Kuen (David) Kwong
发明人： Kwok Kuen (David) Kwong
IPC分类号： H02H9/00 , H01C1/00 , H02H1/04 , H02H3/22 , H02H9/06
CPC分类号： H02H9/046
摘要： An electro-static-discharge (ESD) protection circuit is a power clamp between a high-voltage power supply VDDH and a ground. The power clamp protects high-voltage transistors in a first core and low-voltage transistors in a second core using a low-voltage clamp transistor. The low-voltage transistors have lower power-supply and snap-back voltages than the high-voltage transistors. Trigger circuits are triggered when an ESD pulse is detected on VDDH. One trigger circuit enables a gate of the low-voltage clamp transistor. A series of diodes connected between VDDH and a drain of the clamp transistor prevents latch up or snap-back during normal operation. During an ESD pulse, the series of diodes is briefly bypassed by a p-channel bypass transistor when a second trigger circuit activates an initial trigger transistor which pulses the gate of the p-channel bypass transistor low for a period of time set by an R-C network in the second trigger circuit.
摘要翻译：静电放电（ESD）保护电路是高压电源VDDH和地之间的电源钳位。功率钳使用低电压钳位晶体管保护第一个内核中的高压晶体管和第二个内核中的低压晶体管。低压晶体管具有比高压晶体管更低的电源和快速反应电压。当在VDDH上检测到ESD脉冲时触发电路。一个触发电路使能低压钳位晶体管的栅极。连接在VDDH和钳位晶体管的漏极之间的一系列二极管可以防止在正常工作期间闭锁或回跳。在ESD脉冲期间，当第二触发电路激活初始触发晶体管时，由p沟道旁路晶体管短暂地旁路一系列二极管，该初始触发晶体管将p沟道旁路晶体管的栅极置为低电平，由RC设置的时间段网络中的第二个触发电路。

6. 发明申请

US20090134923A1 ZERO-DELAY BUFFER WITH COMMON-MODE EQUALIZER FOR INPUT AND FEEDBACK DIFFERENTIAL CLOCKS INTO A PHASE-LOCKED LOOP (PLL) 有权
标题翻译：具有用于输入和反馈差分时钟的共模均衡器的零延迟缓冲器进入相位锁定环路（PLL）
公开(公告)号：US20090134923A1
公开(公告)日：2009-05-28
申请号：US11944545
申请日：2007-11-23
申请人： Kwok Kuen (David) Kwong , Ho Ming (Karen) Wan
发明人： Kwok Kuen (David) Kwong , Ho Ming (Karen) Wan
IPC分类号： H03L7/089 , H03L7/085 , H03K3/00
CPC分类号： H03L7/081 , H03L7/0891
摘要： A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.
摘要翻译：零延迟时钟发生器具有产生反馈时钟并接收参考时钟的锁相环（PLL）。所有时钟均为差分并具有共模电压。外部产生的参考时钟的共模电压可以从内部产生的反馈时钟的共模电压变化。参考时钟和反馈时钟的共模电压差异导致延迟变化，导致产生的时钟的静态相位偏移。共模感测和均衡器感测缓冲参考和反馈时钟的共模电压，并产生控制电压。控制电压调节接收参考和反馈时钟的差分缓冲器的共模电压和延迟。控制电压调节差分缓冲器以匹配缓冲参考和反馈时钟的共模电压。缓冲时钟然后被施加到PLL的相位和频率检测器。

7. 发明授权

US08964436B2 Self-starting transistor-only full-wave rectifier for on-chip AC-DC conversion 有权
标题翻译：用于片内AC-DC转换的自启动晶体管全波整流器
公开(公告)号：US08964436B2
公开(公告)日：2015-02-24
申请号：US13653016
申请日：2012-10-16
申请人： Kwok Kuen (David) Kwong , Kwai Chi Chan , Yunlong Li , Lee L. Yang
发明人： Kwok Kuen (David) Kwong , Kwai Chi Chan , Yunlong Li , Lee L. Yang
IPC分类号： H02M7/5387
CPC分类号： H02M7/219 , H02M2007/2195 , Y02B70/1408
摘要： A transistor-based full-wave bridge rectifier is suitable for low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a bridge across the A.C. inputs to produce an internal power voltage. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors with voltages boosted higher than the peak A.C. voltage. Four diode-connected transistors are connected in parallel with the four p-channel bridge transistors to conduct during initial start-up before the comparator and boost drivers operate. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow. The transistor bridge can be integrated onto system chips.
摘要翻译：基于晶体管的全波桥式整流器适用于诸如由射频识别（RFID）设备接收的低交流输入电压。避免了由桥二极管引起的电压降。四个p沟道晶体管布置在跨过交流输入的桥中以产生内部电源电压。比较器接收交流输入并控制升压驱动器的定时，该电压升压驱动器交替地驱动四个p沟道晶体管的栅极，其电压升高高于峰值交流电压。在比较器和升压驱动器运行之前，四个二极管连接的晶体管与四个p沟道桥式晶体管并联连接，以在初始启动期间导通。基板连接到桥的电源电压一半的电源电压和桥接器的一半的交流输入，以完全关闭晶体管，防止反向电流流动。晶体管桥可以集成到系统芯片上。

8. 发明授权

US08864377B2 CMOS temperature sensor with sensitivity set by current-mirror and resistor ratios without limiting DC bias 有权
标题翻译： CMOS温度传感器，灵敏度由电流镜和电阻比设置，不限制直流偏置
公开(公告)号：US08864377B2
公开(公告)日：2014-10-21
申请号：US13416728
申请日：2012-03-09
申请人： Chun Fai Wong , Leung Ling (Alan) Pun , Kam Hung Chan , Kwok Kuen (David) Kwong
发明人： Chun Fai Wong , Leung Ling (Alan) Pun , Kam Hung Chan , Kwok Kuen (David) Kwong
IPC分类号： G01K7/01
CPC分类号： G01K7/01 , H01L35/32
摘要： An on-chip temperature sensor circuit can be implemented in a standard complementary metal-oxide-semiconductor (CMOS) process using PNP transistors. A pair of transistors have collector currents that are sensitive to voltage, both directly and due to saturation currents. A scaling resistor connects to the emitter of one transistor and its voltage compared to the other transistor's emitter voltage by an error amplifier that generates a bias voltage to current sources that are proportional to absolute temperature since the saturation current sensitivity is subtracted out. The current is mirrored to sink current through a multiplier resistor from an output. An amplifier connected across the multiplier resistor compares a reference voltage to set the DC bias independent of temperature sensitivity. The temperature sensitivity is proportional to the ratio of the multiplier resistor and the scaling resistor, and is multiplied by a mirroring factor. A differential output may also be provided.
摘要翻译：片上温度传感器电路可以在使用PNP晶体管的标准互补金属氧化物半导体（CMOS）工艺中实现。一对晶体管具有对电压敏感的集电极电流，直接和由于饱和电流。缩放电阻连接到一个晶体管的发射极，其电压与另一个晶体管的发射极电压相比较，该误差放大器产生与绝对温度成比例的电流源的偏置电压，因为饱和电流灵敏度被减去。电流被镜像以从输出端吸收电流通过乘法器电阻。连接在乘法器电阻上的放大器将参考电压进行比较，以独立于温度敏感度设置直流偏置。温度灵敏度与乘法器电阻和比例电阻的比例成正比，并乘以镜像因子。还可以提供差分输出。

9. 发明授权

US08797776B2 Diode-less full-wave rectifier for low-power on-chip AC-DC conversion 有权
标题翻译：无二极管全波整流器用于低功耗片上AC-DC转换
公开(公告)号：US08797776B2
公开(公告)日：2014-08-05
申请号：US13652474
申请日：2012-10-16
申请人： Kwok Kuen (David) Kwong , Chun Fai Wong , Leung Ling (Alan) Pun , Ho Ming (Karen) Wan
发明人： Kwok Kuen (David) Kwong , Chun Fai Wong , Leung Ling (Alan) Pun , Ho Ming (Karen) Wan
IPC分类号： H02M7/5387
CPC分类号： H02M7/219 , H02M2007/2195 , Y02B70/1408
摘要： A bridge rectifier operates on low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a transistor bridge across the A.C. inputs to produce an internal power voltage. Another four diode-connected transistors form a start-up diode bridge that generates a comparator power voltage and a reference ground. The start-up diode bridge operates even during initial start-up before the comparator and boost drivers operate. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors in the transistor bridge with voltages boosted higher than the peak A.C. voltage. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow.
摘要翻译：桥式整流器在诸如由射频识别（RFID）设备接收的低交流输入电压下工作。避免了由桥二极管引起的电压降。四个P沟道晶体管布置在跨越交流输入的晶体管桥中以产生内部电源电压。另外四个二极管连接的晶体管形成起始二极管电桥，产生比较器电源电压和参考地。在比较器和升压驱动器运行之前，起动二极管桥即使在初始启动期间也工作。比较器接收交流输入并且控制升压驱动器的定时，其交替地驱动晶体管桥中的四个p沟道晶体管的栅极，其电压升高高于峰值交流电压。基板连接到桥的电源电压一半的电源电压和桥接器的一半的交流输入，以完全关闭晶体管，防止反向电流流动。

10. 发明授权

US08179455B2 Optical black-level cancellation for optical sensors using open-loop sample calibration amplifier 有权
标题翻译：使用开环采样校准放大器的光学传感器的光学黑电平消除
公开(公告)号：US08179455B2
公开(公告)日：2012-05-15
申请号：US12722148
申请日：2010-03-11
申请人： Lap Chi (David) Leung , Yat Tung Lai , Chun Fai Wong , Kam Hung Chan , Kwok Kuen (David) Kwong
发明人： Lap Chi (David) Leung , Yat Tung Lai , Chun Fai Wong , Kam Hung Chan , Kwok Kuen (David) Kwong
IPC分类号： H04N5/217
CPC分类号： H04N5/361 , H04N5/3575
摘要： A Optical Black Pixel (OBP) cancellation circuit corrects offsets in sensors in a CCD/CMOS image sensor when reading dark pixels such at the periphery. A pixel voltage is switched to a sampling capacitor during two phases of the same pixel pulse. Sampling capacitors and feedback capacitors connect to differential inputs of an amplifier. An accumulating capacitor accumulates voltage differences and generates a common-mode voltage that is fed back to another sampling capacitor that stores an amplifier offset. The sampling capacitor and accumulating capacitor and their associated switches form a discrete-time first-order low-pass filter that filters the pixel voltage during the first phase. In the second phase the amplifier acts as a unity-gain amplifier to output an average of the pixel voltage differences generated during an OBP time when blackened or covered pixels are read from the image sensor.
摘要翻译：当在外围读取暗像素时，光学黑色像素（OBP）消除电路校正CCD / CMOS图像传感器中的传感器的偏移。在相同像素脉冲的两个相位期间，将像素电压切换到采样电容器。采样电容器和反馈电容器连接到放大器的差分输入。累积电容器累积电压差并产生反馈到存储放大器偏移的另一采样电容器的共模电压。采样电容器和累加电容器及其相关的开关形成离散时间一阶低通滤波器，其在第一阶段期间对像素电压进行滤波。在第二阶段，放大器用作单位增益放大器，以输出从图像传感器读取黑化或覆盖像素时在OBP时间期间产生的像素电压差的平均值。

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