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1. 发明申请

US20060003500A1 Epitaxial siox barrier/insulation layer 失效
标题翻译：外延型阻氧层/绝缘层
公开(公告)号：US20060003500A1
公开(公告)日：2006-01-05
申请号：US10480403
申请日：2001-06-14
申请人： Chia-Gee Wang , Raphael Tsu , John Lofgren
发明人： Chia-Gee Wang , Raphael Tsu , John Lofgren
IPC分类号： H01L21/00 , H01L27/01
CPC分类号： H01L21/76251 , B82Y10/00 , H01L21/76248 , H01L2924/0002 , H01L2924/00
摘要： A method for producing an insulating or barrier layer (FIG. 1B), useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on a silicon substrate whereby said deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on said deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite. Semiconductor devices are disclosed which comprise said barrier composite.
摘要翻译：一种用于半导体器件的绝缘或阻挡层（图1B）的制造方法，包括在硅衬底上沉积硅层和至少一个附加元件，由此所述沉积层基本上没有缺陷，使得外延硅基本上没有缺陷可以沉积在所述沉积层上。或者，一个或多个元素，优选包含氧的单层被吸收在硅衬底上。夹在外延硅之间的多个绝缘层形成屏障复合材料。公开了包含所述屏障复合材料的半导体器件。

2. 发明授权

US07023010B2 Si/C superlattice useful for semiconductor devices 失效
标题翻译： Si / C超晶格可用于半导体器件
公开(公告)号：US07023010B2
公开(公告)日：2006-04-04
申请号：US10823990
申请日：2004-04-14
申请人： Chia Gee Wang , Raphael Tsu
发明人： Chia Gee Wang , Raphael Tsu
IPC分类号： H01L29/06
CPC分类号： H01L29/768 , H01L33/06
摘要： A Si/C superlattice useful for semiconductor devices comprises a plurality of epitaxially grown silicon layers alternating with carbon layers respectively adsorbed on surfaces of said silicon layers. Structures and devices comprising the superlattice and methods are described.
摘要翻译：可用于半导体器件的Si / C超晶格包括与分别吸附在所述硅层表面上的碳层交替的多个外延生长的硅层。描述了包括超晶格和方法的结构和器件。

3. 发明授权

US07105895B2 Epitaxial SiOx barrier/insulation layer 失效
标题翻译：外延SiOx阻隔层/绝缘层
公开(公告)号：US07105895B2
公开(公告)日：2006-09-12
申请号：US10480403
申请日：2001-06-14
申请人： Chia-Gee Wang , Raphael Tsu , John Clay Lofgren
发明人： Chia-Gee Wang , Raphael Tsu , John Clay Lofgren
IPC分类号： H01L23/58 , H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/76251 , B82Y10/00 , H01L21/76248 , H01L2924/0002 , H01L2924/00
摘要： A method for producing an insulating or barrier layer (FIG. 1B), useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on a silicon substrate whereby said deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on said deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite. Semiconductor devices are disclosed which comprise said barrier composite.
摘要翻译：一种用于半导体器件的绝缘或阻挡层（图1B）的制造方法，包括在硅衬底上沉积硅层和至少一个附加元件，由此所述沉积层基本上没有缺陷，使得外延硅基本上没有缺陷可以沉积在所述沉积层上。或者，一个或多个元素，优选包含氧的单层被吸收在硅衬底上。夹在外延硅之间的多个绝缘层形成屏障复合材料。公开了包含所述屏障复合材料的半导体器件。

4. 发明授权

US06376337B1 Epitaxial SiOx barrier/insulation layer 失效
标题翻译：外延SiOx阻隔层/绝缘层
公开(公告)号：US06376337B1
公开(公告)日：2002-04-23
申请号：US09188586
申请日：1998-11-09
申请人： Chia-Gee Wang , Raphael Tsu , John Clay Lofgren
发明人： Chia-Gee Wang , Raphael Tsu , John Clay Lofgren
IPC分类号： H01L2120
CPC分类号： H01L21/76251 , B82Y10/00 , H01L21/76248 , H01L2924/0002 , H01L2924/00
摘要： A method for producing an insulating or barrier layer, useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on said silicon substrate whereby said deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on said deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite. Semiconductor devices are disclosed which comprise said barrier composite.
摘要翻译：一种制造用于半导体器件的绝缘或阻挡层的方法，包括在所述硅衬底上沉积硅层和至少一个附加元件，由此所述沉积层基本上没有缺陷，使得基本上没有缺陷的外延硅可以是沉积在所述沉积层上。或者，一个或多个元素，优选包含氧的单层被吸收在硅衬底上。夹在外延硅之间的多个绝缘层形成屏障复合材料。公开了包含所述屏障复合材料的半导体器件。

5. 发明授权

US09812527B2 Growth of semiconductors on hetero-substrates using graphene as an interfacial layer 有权
公开(公告)号：US09812527B2
公开(公告)日：2017-11-07
申请号：US15463804
申请日：2017-03-20
申请人： Yong Zhang , Raphael Tsu , Naili Yue
发明人： Yong Zhang , Raphael Tsu , Naili Yue
IPC分类号： H01L21/00 , H01L29/16 , H01L29/165 , H01L21/02
CPC分类号： H01L29/16 , H01L21/0242 , H01L21/02444 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/0259 , H01L21/02598 , H01L21/0262 , H01L21/02631 , H01L21/02658 , H01L29/1606 , H01L29/165
摘要： Graphene is used as an interfacial layer to grow Si and other semiconductors or crystalline materials including two-dimensional Si and other structures on any foreign substrate that can withstand the growth temperature without the limitation matching condition typically required for epitaxial growth.

6. 发明授权

US09601579B2 Growth of semiconductors on hetero-substrates using graphene as an interfacial layer 有权
公开(公告)号：US09601579B2
公开(公告)日：2017-03-21
申请号：US14786029
申请日：2014-05-27
申请人： Yong Zhang , Raphael Tsu , Naili Yue
发明人： Yong Zhang , Raphael Tsu , Naili Yue
IPC分类号： H01L21/20 , H01L29/16 , H01L21/02 , H01L29/165
CPC分类号： H01L29/16 , H01L21/0242 , H01L21/02444 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/0259 , H01L21/02598 , H01L21/0262 , H01L21/02631 , H01L21/02658 , H01L29/1606 , H01L29/165
摘要： Graphene is used as an interfacial layer to grow Si and other semiconductors or crystalline materials including two-dimensional Si and other structures on any foreign substrate that can withstand the growth temperature without the limitation matching condition typically required for epitaxial growth.

7. 发明授权

US5051786A Passivated polycrystalline semiconductors quantum well/superlattice structures fabricated thereof 失效
标题翻译：其制造的钝化多晶半导体量子阱/超晶格结构
公开(公告)号：US5051786A
公开(公告)日：1991-09-24
申请号：US426571
申请日：1989-10-24
申请人： Edward H. Nicollian , Arnold Reiman , Raphael Tsu
发明人： Edward H. Nicollian , Arnold Reiman , Raphael Tsu
IPC分类号： H01L21/324 , H01L29/15 , H01L29/16
CPC分类号： H01L21/324 , H01L21/3245 , H01L29/154 , H01L29/1604
摘要： The internal grain boundaries and intergranular spaces of polycrystalline semiconductor material may be passivated with an amorphous material, to substantially eliminate the dangling bonds at the internal grain boundaries. The passivated polycrystalline material of the present invention exhibits a lower electrically active defect density at the grain boundaries and intergranular space compared to unpassivated polycrystalline material. Moreover, large classes of amorphous passivating materials may be used for each known semiconductor material so that the passivating process may be readily adapted to existing process parameters and other device constraints. Passivated polycrystalline material may be employed to form the well or low energy bandgap layer of a quantum well device or superlattice, while still maintaining the required tunneling effect. By freeing quantum well devices from the requirement to use monocrystalline well material deeper wells may be produced, and a wider range of materials may be used, with high yields and low cost processes.
摘要翻译：多晶半导体材料的内部晶界和晶间空间可以用无定形材料钝化，以基本上消除内部晶界处的悬挂键。与未钝化的多晶材料相比，本发明的钝化多晶材料在晶界和晶间间隙处表现出较低的电活性缺陷密度。而且，对于每种已知的半导体材料，可以使用大类非晶体钝化材料，使得钝化工艺可以容易地适应现有工艺参数和其它器件限制。可以采用钝化多晶材料来形成量子阱器件或超晶格的阱或低能带隙层，同时仍然保持所需的隧道效应。通过将量子阱器件从使用单晶阱材料的要求释放，可以生产较深的阱，并且可以使用更宽范围的材料，具有高产率和低成本的工艺。

8. 发明授权

US06239450B1 Negative differential resistance device based on tunneling through microclusters, and method therefor 失效
标题翻译：基于通过微型集群隧穿的负差动电阻装置及其方法
公开(公告)号：US06239450B1
公开(公告)日：2001-05-29
申请号：US09231429
申请日：1999-01-14
申请人： James F. Harvey , Robert A. Lux , Raphael Tsu
发明人： James F. Harvey , Robert A. Lux , Raphael Tsu
IPC分类号： H01L2100
CPC分类号： B82Y10/00 , H01L29/32 , H01L29/882
摘要： A solid state electronic device exhibiting negative differential resistance is fabricated by depositing a thin layer of amorphous silicon on a single crystal substrate, doped N+. The amorphous silicon is simultaneously crystallized and oxidized in a dry N2 and O2 mixture. The result is a layer of amorphous SiO2 surrounding microclusters of crystalline silicon. A layer of polycrystalline silicon is deposited to a thickness of approximately 0.5 micron. Ohmic metal contacts are made to the top and bottom. These active layers are isolated by insulating SiO2. A bias voltage applied between the metal contacts results in negative differential resistance due to tunneling through resonant energy levels in microclusters.
摘要翻译：通过在掺杂N +的单晶衬底上沉积非晶硅薄层来制造显示负差分电阻的固态电子器件。非晶硅同时结晶并在干燥的N 2和O 2混合物中氧化。结果是结晶硅周围的微结构的非晶SiO 2层。一层多晶硅沉积到约0.5微米的厚度。欧姆金属触点制成顶部和底部。这些有源层通过绝缘SiO 2来隔离。施加在金属触点之间的偏置电压导致由于在微型集群中通过谐振能级的隧穿而导致的负差分电阻。

9. 发明授权

US5324965A Light emitting diode with electro-chemically etched porous silicon 失效
标题翻译：具有电化学蚀刻多孔硅的发光二极管
公开(公告)号：US5324965A
公开(公告)日：1994-06-28
申请号：US39652
申请日：1993-03-26
申请人： Michael F. Tompsett , Raphael Tsu
发明人： Michael F. Tompsett , Raphael Tsu
IPC分类号： H01L33/34 , H01L33/38 , H01L33/42 , H01L33/00
CPC分类号： H01L33/38 , H01L33/346 , H01L2933/0016 , H01L33/42
摘要： A light emitting diode comprising microporous silicon of one conductivity type forming a PN junction with silicon of the opposite conductivity type and electrodes respectively connected to said regions, at least one of the electrodes being transparent.
摘要翻译：一种发光二极管，包括一种导电类型的微孔硅，其形成具有相反导电类型的硅的PN结和分别连接到所述区的电极，至少一个电极是透明的。

10. 发明授权

US5216262A Quantum well structures useful for semiconductor devices 失效
标题翻译：用于半导体器件的量子阱结构
公开(公告)号：US5216262A
公开(公告)日：1993-06-01
申请号：US844725
申请日：1992-03-02
申请人： Raphael Tsu
发明人： Raphael Tsu
IPC分类号： H01L29/15 , H01L29/51
CPC分类号： H01L29/513 , B82Y10/00 , H01L29/151 , H01L29/154 , H01L29/51
摘要： A quantum well structure useful for semiconducting devices comprises two barrier regions and a thin epitaxially grown monocrystalline semiconductor material quantum well sandwiched between said barrier regions. Each barrier region consists essentially of alternate strain layers forming a superlattice, each of said layers being thinner than said quantum well. The layers are so thin that no defects are generated as a result of the release of stored strain energy.
摘要翻译：可用于半导体器件的量子阱结构包括两个势垒区和一个薄的外延生长的单晶半导体材料量子阱夹在所述势垒区之间。每个阻挡区域基本上由形成超晶格的交替应变层组成，每个所述层都比所述量子阱薄。这些层非常薄，由于释放存储的应变能而不会产生缺陷。

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