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1. 发明授权

US09773784B2 Semiconductor structure and method for manufacturing the same 有权
公开(公告)号：US09773784B2
公开(公告)日：2017-09-26
申请号：US13594296
申请日：2012-08-24
申请人： Chieh-Chih Chen , Cheng-Chi Lin , Shih-Chin Lien , Shyi-Yuan Wu
发明人： Chieh-Chih Chen , Cheng-Chi Lin , Shih-Chin Lien , Shyi-Yuan Wu
IPC分类号： H01L29/78 , H01L27/088 , H01L21/761 , H01L29/66 , H01L21/8234 , H01L29/423 , H01L29/06 , H01L29/08
CPC分类号： H01L27/088 , H01L21/761 , H01L21/823418 , H01L21/823481 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a device region, a first doped region and a gate structure. The first doped region is formed in the substrate adjacent to the device region. The gate structure is on the first doped region. The first doped region is overlapped the gate structure.

2. 发明授权

US08610209B2 Ultra-high voltage N-type-metal-oxide-semiconductor (UHV NMOS) device and methods of manufacturing the same 有权
公开(公告)号：US08610209B2
公开(公告)日：2013-12-17
申请号：US13070819
申请日：2011-03-24
申请人： Chieh-Chih Chen , Cheng-Chi Lin , Chen-Yuan Lin , Shih-Chin Lien , Shyi-Yuan Wu
发明人： Chieh-Chih Chen , Cheng-Chi Lin , Chen-Yuan Lin , Shih-Chin Lien , Shyi-Yuan Wu
IPC分类号： H01L27/088
CPC分类号： H01L29/66477 , H01L29/0634 , H01L29/0646 , H01L29/0653 , H01L29/0692 , H01L29/0878 , H01L29/1083 , H01L29/41758 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer.

3. 发明申请

US20140054656A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20140054656A1
公开(公告)日：2014-02-27
申请号：US13594296
申请日：2012-08-24
申请人： Chieh-Chih Chen , Cheng-Chi Lin , Shih-Chin Lien , Shyi-Yuan Wu
发明人： Chieh-Chih Chen , Cheng-Chi Lin , Shih-Chin Lien , Shyi-Yuan Wu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/088 , H01L21/761 , H01L21/823418 , H01L21/823481 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a device region, a first doped region and a gate structure. The first doped region is formed in the substrate adjacent to the device region. The gate structure is on the first doped region. The first doped region is overlapped the gate structure.
摘要翻译：提供半导体结构及其制造方法。半导体结构包括衬底，器件区域，第一掺杂区域和栅极结构。第一掺杂区域形成在与器件区域相邻的衬底中。栅极结构在第一掺杂区域上。第一掺杂区域与栅极结构重叠。

4. 发明申请

US20130020680A1 SEMICONDUCTOR STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130020680A1
公开(公告)日：2013-01-24
申请号：US13185948
申请日：2011-07-19
申请人： Chieh-Chih Chen , Cheng-Chi Lin , Shih-Chin Lien , Shyi-Yuan Wu
发明人： Chieh-Chih Chen , Cheng-Chi Lin , Shih-Chin Lien , Shyi-Yuan Wu
IPC分类号： H01L29/866 , H01L21/22
CPC分类号： H01L29/66106 , H01L27/0629 , H01L29/0646 , H01L29/0649 , H01L29/1083 , H01L29/36 , H01L29/7835 , H01L29/866
摘要： A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion.
摘要翻译：提供半导体结构及其制造方法。半导体结构包括二极管。二极管包括第一掺杂区，第二掺杂区和第三掺杂区。第一掺杂区域和第三掺杂区域具有第一导电类型。第二掺杂区具有与第一导电类型相反的第二导电类型。第二掺杂区域和第三掺杂区域通过第一掺杂区域彼此分离。第三掺杂区域具有彼此相邻的第一部分和第二部分。第一部分和第二部分分别与第二掺杂区域相邻并远离第二掺杂区域。第一部分的掺杂剂浓度大于第二部分的掺杂剂浓度。

5. 发明授权

US08564099B2 Semiconductor structure and a method for manufacturing the same 有权
公开(公告)号：US08564099B2
公开(公告)日：2013-10-22
申请号：US13185948
申请日：2011-07-19
申请人： Chieh-Chih Chen , Cheng-Chi Lin , Shih-Chin Lien , Shyi-Yuan Wu
发明人： Chieh-Chih Chen , Cheng-Chi Lin , Shih-Chin Lien , Shyi-Yuan Wu
IPC分类号： H01L29/866
CPC分类号： H01L29/66106 , H01L27/0629 , H01L29/0646 , H01L29/0649 , H01L29/1083 , H01L29/36 , H01L29/7835 , H01L29/866
摘要： A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion.

6. 发明申请

US20120241861A1 Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same 有权
标题翻译：超高压N型金属氧化物半导体（UHV NMOS）器件及其制造方法
公开(公告)号：US20120241861A1
公开(公告)日：2012-09-27
申请号：US13070819
申请日：2011-03-24
申请人： Chieh-Chih Chen , Cheng-Chi Lin , Chen-Yuan Lin , Shih-Chin Lien , Shyi-Yuan Wu
发明人： Chieh-Chih Chen , Cheng-Chi Lin , Chen-Yuan Lin , Shih-Chin Lien , Shyi-Yuan Wu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66477 , H01L29/0634 , H01L29/0646 , H01L29/0653 , H01L29/0692 , H01L29/0878 , H01L29/1083 , H01L29/41758 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer.
摘要翻译：提供了具有改进性能的超高电压n型金属氧化物半导体（UHV NMOS）器件及其制造方法。 UHV NMOS包括P型材料的衬底; 设置在所述基板的一部分中的第一高压N阱（HVNW）区域; 与第一HVNW区域的一侧相邻的源极和体积p阱（PW），源极和体积PW包括源极和体积; 从源极和体积PW延伸到第一HVNW区域的一部分的栅极，以及设置在与栅极相对的第一HVNW区域的另一部分内的漏极; 设置在第一HVNW区域内的P顶层，位于漏极与源极和体PW之间的P顶层; 以及形成在P顶层上的n型注入层。

7. 发明授权

US08749016B2 High voltage MOS device and method for making the same 有权
标题翻译：高压MOS器件及其制造方法
公开(公告)号：US08749016B2
公开(公告)日：2014-06-10
申请号：US12899152
申请日：2010-10-06
申请人： Chieh-Chih Chen , Cheng-Chi Lin , Chen-Yuan Lin , Shih-Chin Lien , Shyi-Yuan Wu
发明人： Chieh-Chih Chen , Cheng-Chi Lin , Chen-Yuan Lin , Shih-Chin Lien , Shyi-Yuan Wu
IPC分类号： H01L29/06
CPC分类号： H01L29/66681 , H01L27/0629 , H01L27/0922 , H01L29/0607 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/1083 , H01L29/1087 , H01L29/402 , H01L29/404 , H01L29/42368 , H01L29/7816
摘要： A high-voltage metal-oxide-semiconductor (HVMOS) device may include a source, a drain, a gate positioned proximate to the source, a drift region disposed substantially between the drain and a region of the gate and the source, and a self shielding region disposed proximate to the drain. A corresponding method is also provided.
摘要翻译：高压金属氧化物半导体（HVMOS）器件可以包括源极，漏极，位于源极附近的栅极，基本上设置在漏极与栅极和源极区域之间的漂移区域，以及自屏蔽区域设置在漏极附近。还提供了相应的方法。

8. 发明申请

US20120086052A1 HIGH VOLTAGE MOS DEVICE AND METHOD FOR MAKING THE SAME 有权
标题翻译：高电压MOS器件及其制造方法
公开(公告)号：US20120086052A1
公开(公告)日：2012-04-12
申请号：US12899152
申请日：2010-10-06
申请人： Chieh-Chih Chen , Cheng-Chi Lin , Chen-Yuan Lin , Shih-Chin Lien , Shyi-Yuan Wu
发明人： Chieh-Chih Chen , Cheng-Chi Lin , Chen-Yuan Lin , Shih-Chin Lien , Shyi-Yuan Wu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66681 , H01L27/0629 , H01L27/0922 , H01L29/0607 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/1083 , H01L29/1087 , H01L29/402 , H01L29/404 , H01L29/42368 , H01L29/7816
摘要： A high-voltage metal-oxide-semiconductor (HVMOS) device may include a source, a drain, a gate positioned proximate to the source, a drift region disposed substantially between the drain and a region of the gate and the source, and a self shielding region disposed proximate to the drain. A corresponding method is also provided.
摘要翻译：高压金属氧化物半导体（HVMOS）器件可以包括源极，漏极，位于源极附近的栅极，基本上设置在漏极与栅极和源极区域之间的漂移区域，以及自屏蔽区域设置在漏极附近。还提供了相应的方法。

9. 发明授权

US08525243B2 Single gate semiconductor device 有权
标题翻译：单门半导体器件
公开(公告)号：US08525243B2
公开(公告)日：2013-09-03
申请号：US13180236
申请日：2011-07-11
申请人： Cheng-Chi Lin , Shih-Chin Lien , Chin-Pen Yeh , Shyi-Yuan Wu
发明人： Cheng-Chi Lin , Shih-Chin Lien , Chin-Pen Yeh , Shyi-Yuan Wu
IPC分类号： H01L27/105
CPC分类号： H01L29/6659 , H01L27/11558 , H01L29/1083 , H01L29/66825 , H01L29/7833 , H01L29/788
摘要： A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor.
摘要翻译：半导体器件在栅极的两侧具有栅极多个掺杂区域。栅极可以由晶体管和电容器共享。

10. 发明授权

US08487360B2 Semiconductor memory devices with high gate coupling ratio and methods of manufacturing the same 有权
标题翻译：具有高栅极耦合比的半导体存储器件及其制造方法相同
公开(公告)号：US08487360B2
公开(公告)日：2013-07-16
申请号：US12876711
申请日：2010-09-07
申请人： Cheng-Chi Lin , Shih-Chin Lien , Shyi-Yuan Wu , Chin-Pen Yeh
发明人： Cheng-Chi Lin , Shih-Chin Lien , Shyi-Yuan Wu , Chin-Pen Yeh
IPC分类号： H01L27/112
CPC分类号： H01L27/0629 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A semiconductor memory device includes a substrate of a first impurity type, a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type, a second well region of the first impurity type in the substrate, a patterned first dielectric layer on the substrate extending over the first and second well regions, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure may include a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, wherein the first section and the second section intersects each other in a cross pattern. The patterned second gate structure may include at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure.
摘要翻译：半导体存储器件包括：第一杂质型衬底，衬底中第二杂质类型的第一阱区，第二杂质型不同于第一杂质型;衬底中第一杂质型第二阱区; 在衬底上的图案化的第一介电层延伸在第一和第二阱区上，图案化的第一介电层上的图案化的第一栅极结构，图案化的第一栅极结构上的图案化的第二介电层，以及图案化的第二栅极结构图案化的第二介电层。图案化的第一栅极结构可以包括沿第一方向延伸的第一部分和沿与第一部分正交的第二方向延伸的第二部分，其中第一部分和第二部分以交叉图案彼此相交。图案化的第二栅极结构可以包括在图案化的第一栅极结构的第一部分上的第一方向上延伸的第一部分或者在图案化的第一栅极结构的第二部分上沿第二方向延伸的第二部分中的至少一个。

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