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1. 发明申请

US20120250758A1 METHOD AND APPARATUS FOR FRAME MEMORY COMPRESSION 有权
标题翻译：框架记忆压缩的方法和装置
公开(公告)号：US20120250758A1
公开(公告)日：2012-10-04
申请号：US13178510
申请日：2011-07-08
申请人： Fan-Di Jou , Chih-Hsu Yen , Chun-Lung Lin , Tian-Jian Wu
发明人： Fan-Di Jou , Chih-Hsu Yen , Chun-Lung Lin , Tian-Jian Wu
IPC分类号： H04N7/12
CPC分类号： H04N19/00121 , H04N19/126 , H04N19/13 , H04N19/132 , H04N19/146 , H04N19/174
摘要： A method for frame memory compression divides each of a plurality of image frames in a frame memory into a plurality of blocks for taking a block as a compression unit. It quantizes a plurality of pixel values inside the block according to a predefined parameter, thereby generating a quantized block and a plurality of removed bits from the binary representation of the plurality of pixel values. A predictor is used to produce a residual block for the quantized block. A variable length encoder takes the residual block as an input and produces a coded bitstream. A packing unit is used to take the coded bitstream and the number of removed bits generated by the quantizer as inputs, so as to produce an entire codeword sequence of the block that meets a target bit rate by using a structure called group of blocks (GOB) to flexibly share available spaces of the blocks in the same GOB.
摘要翻译：一种用于帧存储器压缩的方法将帧存储器中的多个图像帧中的每一个划分成用于获取块作为压缩单元的多个块。它根据预定义的参数对块内的多个像素值进行量化，从而从多个像素值的二进制表示中生成量化块和多个去除的位。预测器用于产生量化块的残差块。可变长度编码器将残差块作为输入并产生编码比特流。使用打包单元将编码比特流和由量化器生成的去除比特数作为输入，以便通过使用称为块组（GOB）的结构来产生满足目标比特率的块的整个码字序列）来灵活地共享相同GOB中块的可用空间。

2. 发明授权

US08280938B2 Semi-sequential Galois Field multiplier and the method for performing the same 有权
标题翻译：半顺序伽罗瓦域乘法器及其执行方法
公开(公告)号：US08280938B2
公开(公告)日：2012-10-02
申请号：US12346787
申请日：2008-12-30
申请人： Chih-Hsu Yen
发明人： Chih-Hsu Yen
IPC分类号： G06F17/10
CPC分类号： G06F7/724
摘要： Disclosed are a semi-sequential Galois field GF(2n) multiplier and the method thereof. The GF(2n) multiplier comprises two ground field multipliers over GF(2m), at least a constant multiplier, and multiple GF(2m) adders. The high-order and low-order elements from a composite field GF((2m)2) for one operand of one GF(2n) multiplication are inputted in parallel into the two ground GF(2m) multipliers, respectively. The high-order and low-order elements from the composite field of another operand of the GF(2n) multiplication are sequentially inputted into the two ground GF(2m) multipliers. As such, multiple partial products are generated. The constant multiplication and additions are performed on the multiple partial products through the constant multiplier and the GF(2m) adders. This generates a high-order element and a low-order element of the composite field GF((2m)2). After mapping these two elements of GF((2m)2) back to GF(2n), the GF(2n) multiplication is done.
摘要翻译：公开了半顺序伽罗瓦域GF（2n）乘法器及其方法。 GF（2n）乘法器包括GF（2m）上的两个地面场乘法器，至少一个常数乘法器和多个GF（2m）加法器。对于一个GF（2n）乘法的一个操作数的复合字段GF（（2m）2）的高阶和低阶元素分别并入两个GF（2m）乘法器。来自GF（2n）乘法的另一个操作数的复合域的高阶和低阶元素被顺序地输入到两个GF（2m）乘法器中。因此，产生多个部分产品。通过常数乘法器和GF（2m）加法器对多个部分乘积执行恒定乘法和加法。这产生复合字段GF（（2m）2）的高阶元素和低阶元素。将GF（（2m）2）的这两个元素映射到GF（2n）之后，完成GF（2n）乘法。

3. 发明授权

US07970130B2 Low-latency method and apparatus of GHASH operation for authenticated encryption Galois Counter Mode 有权
标题翻译：用于认证加密伽罗瓦计数器模式的低延迟方法和GHASH操作的装置
公开(公告)号：US07970130B2
公开(公告)日：2011-06-28
申请号：US11858906
申请日：2007-09-21
申请人： Chih-Hsu Yen
发明人： Chih-Hsu Yen
IPC分类号： H04K1/00 , H04L9/00 , H04L1/00
CPC分类号： H04L9/0637 , G06F7/724 , H04L9/0643
摘要： Disclosed is a low-latency method and apparatus of GHASH operation for authenticated encryption Galois Counter Mode (GCM), which simultaneously computes three interim values respectively yielded from the additional authenticated data A, the ciphertext C, and the hash key H defined in the GCM. Then, the output of the GHASH operation may be derived. Assuming that A has m blocks and C has n blocks, this disclosure performs the GHASH operation with max {m,n}+1 steps. The input order for the additional authenticated data A and the ciphertext C may be independent. A disordered sequence for the additional authenticated data A and the ciphertext C may also be accepted by this disclosure. This allows the applications in GCM to be more flexible.
摘要翻译：公开了一种用于认证加密伽罗瓦计数器模式（GCM）的低延迟方法和装置，其同时计算从附加认证数据A，密文C和在GCM中定义的散列密钥H分别产生的三个中间值。然后，可以导出GHASH操作的输出。假设A具有m个块并且C具有n个块，则该公开以最大{m，n} +1个步骤来执行GHASH操作。附加认证数据A和密文C的输入顺序可以是独立的。附加认证数据A和密文C的无序序列也可被本公开所接受。这样可以使GCM中的应用更加灵活。

4. 发明申请

US20100115017A1 Semi-Sequential Galois Field Multiplier And The Method For Performing The Same 有权
标题翻译：半顺序伽罗瓦域乘法器及其执行方法
公开(公告)号：US20100115017A1
公开(公告)日：2010-05-06
申请号：US12346787
申请日：2008-12-30
申请人： Chih-Hsu Yen
发明人： Chih-Hsu Yen
IPC分类号： G06F17/10
CPC分类号： G06F7/724
摘要： Disclosed are a semi-sequential Galois field GF(2n) multiplier and the method thereof. The GF(2n) multiplier comprises two ground field multipliers over GF(2m), at least a constant multiplier, and multiple GF(2m) adders. The high-order and low-order elements from a composite field GF((2m)2) for one operand of one GF(2n) multiplication are inputted in parallel into the two ground GF(2m) multipliers, respectively. The high-order and low-order elements from the composite field of another operand of the GF(2n) multiplication are sequentially inputted into the two ground GF(2m) multipliers. As such, multiple partial products are generated. The constant multiplication and additions are performed on the multiple partial products through the constant multiplier and the GF(2m) adders. This generates a high-order element and a low-order element of the composite field GF((2m)2). After mapping these two elements of GF((2m)2) back to GF(2n), the GF(2n) multiplication is done.
摘要翻译：公开了半顺序伽罗瓦域GF（2n）乘法器及其方法。 GF（2n）乘法器包括GF（2m）上的两个地面场乘法器，至少一个常数乘法器和多个GF（2m）加法器。对于一个GF（2n）乘法的一个操作数的复合字段GF（（2m）2）的高阶和低阶元素分别并入两个GF（2m）乘法器。来自GF（2n）乘法的另一个操作数的复合域的高阶和低阶元素被顺序地输入到两个GF（2m）乘法器中。因此，产生多个部分产品。通过常数乘法器和GF（2m）加法器对多个部分乘积执行恒定乘法和加法。这产生复合字段GF（（2m）2）的高阶元素和低阶元素。将GF（（2m）2）的这两个元素映射到GF（2n）之后，完成GF（2n）乘法。

5. 发明授权

US08767823B2 Method and apparatus for frame memory compression 有权
标题翻译：用于帧存储器压缩的方法和装置
公开(公告)号：US08767823B2
公开(公告)日：2014-07-01
申请号：US13178510
申请日：2011-07-08
申请人： Fan-Di Jou , Chih-Hsu Yen , Chun-Lung Lin , Tian-Jian Wu
发明人： Fan-Di Jou , Chih-Hsu Yen , Chun-Lung Lin , Tian-Jian Wu
IPC分类号： H04N7/12 , H04N7/26
CPC分类号： H04N19/00121 , H04N19/126 , H04N19/13 , H04N19/132 , H04N19/146 , H04N19/174
摘要： A method for frame memory compression divides each of a plurality of image frames in a frame memory into a plurality of blocks and quantizes a plurality of pixel values inside each block according to a predefined parameter, thereby generating a quantized block and a plurality of removed bits from the binary representation of the plurality of pixel values. A predictor is used to produce a residual block for the quantized block. A variable length encoder takes the residual block as an input and produces a coded bitstream. A packing unit is used to take the coded bitstream and the number of removed bits generated by the quantizer as inputs, so as to produce an entire codeword sequence of the block that meets a target bit rate by using a structure called group of blocks (GOB) to flexibly share available spaces of the blocks in the same GOB.
摘要翻译：一种用于帧存储器压缩的方法，将帧存储器中的多个图像帧中的每一个划分为多个块，并根据预定参数量化每个块内的多个像素值，从而生成量化块和多个去除位从多个像素值的二进制表示。预测器用于产生量化块的残差块。可变长度编码器将残差块作为输入并产生编码比特流。使用打包单元将编码比特流和由量化器生成的去除比特数作为输入，以便通过使用称为块组（GOB）的结构来产生满足目标比特率的块的整个码字序列）来灵活地共享相同GOB中块的可用空间。

6. 发明申请

US20090080646A1 Method And Architecture For Parallel Calculating Ghash Of Galois Counter Mode 审中-公开
标题翻译：用于并行计算Galois计数器模式的Ghash的方法和架构
公开(公告)号：US20090080646A1
公开(公告)日：2009-03-26
申请号：US12135210
申请日：2008-06-09
申请人： Chih-Hsu Yen
发明人： Chih-Hsu Yen
IPC分类号： H04L9/28 , G06F7/00
CPC分类号： H04L9/3236 , G06F7/724 , H04L9/0637 , H04L9/0643 , H04L2209/125
摘要： Disclosed is a method and architecture for parallel calculating GHASH of Galois Counter Mode (GCM), which regards the additional authenticated data A and the ciphertext C defined in the GCM as a single data M with an input order of a sequence M1M2 . . . Mm-1, and arranges the final output of the GHASH into a combination of the sequence M1M2 . . . Mm-1 and the hash key H. Then, the combined form for the final output is further divided into two odd and even parallel calculating parts. According to the two parallel calculating parts and the hash key H, the final output of the GHASH operation is calculated. This invention may calculate the additional authenticated data A and the ciphertext C in parallel. It may also calculate the even-order input data and odd-order input data in parallel.
摘要翻译：公开了用于并行计算Galois计数器模式（GCM）的GHASH的方法和架构，其将附加认证数据A和在GCM中定义的密文C视为具有序列M1M2的输入顺序的单个数据M. 。。 Mm-1，并将GHASH的最终输出排列为序列M1M2的组合。。。 Mm-1和散列键H.然后，用于最终输出的组合形式进一步分为两个奇数和偶数并行计算部分。根据两个并行计算部分和散列键H，计算GHASH操作的最终输出。本发明可并行地计算附加认证数据A和密文C. 也可以并行计算偶数输入数据和奇数输入数据。

7. 发明申请

US20080279368A1 Low-Latency Method And Apparatus Of Ghash Operation For Authenticated Encryption Galois Counter Mode 有权
标题翻译：用于认证加密伽罗瓦计数器模式的Ghash操作的低延迟方法和装置
公开(公告)号：US20080279368A1
公开(公告)日：2008-11-13
申请号：US11858906
申请日：2007-09-21
申请人： Chih-Hsu Yen
发明人： Chih-Hsu Yen
IPC分类号： H04L9/28 , G06F7/523
CPC分类号： H04L9/0637 , G06F7/724 , H04L9/0643
摘要： Disclosed is a low-latency method and apparatus of GHASH operation for authenticated encryption Galois Counter Mode (GCM), which simultaneously computes three interim values respectively yielded from the additional authenticated data A, the ciphertext C, and the hash key H defined in the GCM. Then, the output of the GHASH operation may be derived. Therefore, supposing that A has m blocks and C has n blocks, then this invention performs the GHASH operation with max{m,n}+1 steps. The input order for the additional authenticated data A and the ciphertext C may be independent. A disordered sequence for the additional authenticated data A and the ciphertext C may also be accepted by this invention. This allows the applications in GCM be more flexible.
摘要翻译：公开了一种用于认证加密伽罗瓦计数器模式（GCM）的低延迟方法和装置，其同时计算从附加认证数据A，密文C和在GCM中定义的散列密钥H分别产生的三个中间值。然后，可以导出GHASH操作的输出。因此，假设A具有m个块并且C具有n个块，则本发明以最大{m，n} +1个步骤来执行GHASH操作。附加认证数据A和密文C的输入顺序可以是独立的。附加认证数据A和密文C的无序序列也可以被本发明所接受。这允许GCM中的应用程序更加灵活。

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