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1. 发明授权

US11995184B2 Low-latency digital signature processing with side-channel security 有权
公开(公告)号：US11995184B2
公开(公告)日：2024-05-28
申请号：US17484870
申请日：2021-09-24
申请人： Intel Corporation
发明人： Santosh Ghosh , Andrea Basso , Manoj Sastry
IPC分类号： G06F21/55 , G06F7/72 , G06F21/64 , G06F21/75 , H04L9/00 , H04L9/30 , H04L9/32
CPC分类号： G06F21/556 , G06F7/724 , G06F21/64 , G06F21/75 , H04L9/003 , H04L9/3093 , H04L9/3247 , G06F2207/7223
摘要： A low-latency digital-signature with side-channel security is described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit, wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.

2. 发明公开

US20240039694A1 DEVICE FOR PROCESSING HOMOMORPHICALLY ENCRYPTED DATA 审中-公开
公开(公告)号：US20240039694A1
公开(公告)日：2024-02-01
申请号：US18254132
申请日：2021-11-24
申请人： AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
发明人： Hong YANG , Dee Meng KANG , Ahmad Qaisar Ahmad AL BADAWI , Khin Mi Mi AUNG
IPC分类号： H04L9/00 , G06F9/38 , G06F7/72
CPC分类号： H04L9/008 , G06F9/3875 , G06F7/724
摘要： There is provided a device for processing homomorphically encrypted data. The device includes: inter-line butterfly array blocks, each inter-line butterfly array block including inter-line modulus butterfly units, each inter-line modulus butterfly unit being configured to perform a modulus butterfly operation based on a computation pair of data points received corresponding to a pair of input data points at a same row of a matrix of input data points; intra-line butterfly array blocks, each intra-line butterfly array block including intra-line modulus butterfly units, each intra-line modulus butterfly unit being configured to perform a modulus butterfly operation based on a computation pair of data points received corresponding to a pair of input data points at a same column of the matrix of input data points; and a clock counter communicatively coupled to each inter-line butterfly array block and each intra-line butterfly array block, and configured to output a counter signal for controlling each inter-line butterfly array block and each intra-line butterfly array block to operate with single cycle initiation interval. The matrix of input data points includes columns of input data points, whereby parallel input data points derived from the homomorphically encrypted data are arranged into the columns of input data points. Furthermore, the inter-line butterfly array blocks and the intra-line butterfly array blocks are arranged in series to form a pipeline for processing the matrix of input data points.

3. 发明授权

US11693754B2 Aggregate GHASH-based message authentication code (MAC) over multiple cachelines with incremental updates 有权
公开(公告)号：US11693754B2
公开(公告)日：2023-07-04
申请号：US17685557
申请日：2022-03-03
申请人： Intel Corporation
发明人： David M. Durham , Karanvir S. Grewal , Sergej Deutsch , Michael E. Kounavis
IPC分类号： G06F11/27 , G06F7/72 , G06F11/07 , G06F11/10 , G06F11/14 , G06F11/30 , G06F12/14 , H04L9/06 , H04L9/08 , H04L9/32
CPC分类号： G06F11/27 , G06F7/724 , G06F11/0772 , G06F11/1068 , G06F11/1435 , G06F11/3037 , G06F12/1408 , H04L9/0637 , H04L9/0643 , H04L9/085 , H04L9/3242
摘要： Embodiments are directed to aggregate GHASH-based message authentication code (MAC) over multiple cachelines with incremental updates. An embodiment of a system includes a controller comprising circuitry, the controller to generate an error correction code for a memory line, the memory line comprising a plurality of first data blocks, generate a metadata block corresponding to the memory line, the metadata block comprising the error correction code for the memory line and at least one metadata bit, generate an aggregate GHASH corresponding to a region of memory comprising a cacheline set comprising at least the memory line, encode the first data blocks and the metadata block, encrypt the aggregate GHASH as an aggregate message authentication code (AMAC), provide the encoded first data blocks and the encoded metadata block for storage on a memory module comprising the memory line, and provide the AMAC for storage on a device separate from the memory module.

4. 发明授权

US09971020B1 Radar data buffering 有权
公开(公告)号：US09971020B1
公开(公告)日：2018-05-15
申请号：US15892764
申请日：2018-02-09
申请人： UHNDER, INC.
发明人： Monier Maher , Curtis Davis , Frederick Rush , Aria Eshraghi
IPC分类号： G01S7/35 , G01S13/06 , G01S13/93 , G01S13/64 , G01S7/285
CPC分类号： G01S13/931 , G01S7/032 , G01S7/285 , G01S7/352 , G01S7/354 , G01S7/4017 , G01S7/4021 , G01S13/06 , G01S13/325 , G01S13/34 , G01S13/42 , G01S13/584 , G01S13/64 , G01S13/87 , G01S13/878 , G01S2013/9375 , G01S2013/9378 , G01S2013/9385 , G06F7/724 , G11C11/409
摘要： A radar system includes transmitters and receivers configured for installation and use in a vehicle. The transmitters transmit radio signals. The receivers receive radio signals that include the transmitted radio signals reflected from objects in an environment. Each receiver has an RF front end, an analog-to-digital converter (ADC), a digital signal processor, and a controller. The digital signal processor processes the data from the ADC and stores data samples in a buffer. The buffer operates in several modes defined by the controller. These modes include replay mode, loopback mode, quiet mode, and throttle mode. By controlling the buffer, the same received samples can be processed in multiple ways to generate information on targets at different ranges and velocities. The buffer is read out and the data is processed further to enable the radar system to determine range, velocity, and angle of targets in the environment.

5. 发明申请

US20170244564A1 GENERATING CRYPTOGRAPHIC CHECKSUMS 审中-公开
公开(公告)号：US20170244564A1
公开(公告)日：2017-08-24
申请号：US15504604
申请日：2014-08-19
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： Mats NÄSLUND , Elena DUBROVA , Fredrik LINDQVIST , Göran SELANDER
IPC分类号： H04L9/32 , H04L9/06
CPC分类号： H04L9/3242 , G06F7/724 , H04L1/0061 , H04L9/0643 , H04L2209/34
摘要： A method (500) of generating a cryptographic checksum for a message M(x) is provided. The method comprises pseudo-randomly selecting (502) at least two irreducible polynomials pi(x). Each irreducible polynomial pi(x) is selected based on a first cryptographic key from the set of irreducible polynomials of degree ni over a Galois Field. The method further comprises calculating (503) a generator polynomial p(x) of degree n=formula (I) as a product of the N irreducible polynomials formula (II), and calculating (505) the cryptographic checksum as a first function g of a division of a second function of M(x), ƒ(M(x)), modulo p(x), i.e., g(ƒ(M(x)) mod p(x)). By replacing a standard checksum, such as a Cyclic Redundancy Check (CRC), with a cryptographic checksum, an efficient message authentication is provided. The proposed cryptographic checksum may be used for providing integrity assurance on the message, i.e., for detecting random and intentional message changes, with a known level of security. Further, a corresponding computer program, a corresponding computer program product, and a checksum generator for generating a cryptographic checksum, are provided. Σ i = 1 N  n i ( I ) p i  ( x ) , p  ( x ) = Π i = 1 N  p i  ( x ) , ( II )

6. 发明申请

US20160366109A1 Method and Apparatus for Validating a Transaction between a Plurality of Machines 审中-公开
标题翻译：用于验证多台机器之间的交易的方法和装置
公开(公告)号：US20160366109A1
公开(公告)日：2016-12-15
申请号：US15244985
申请日：2016-08-23
申请人： Peter Lablans
发明人： Peter Lablans
IPC分类号： H04L29/06 , G06Q20/40 , G06Q20/34 , H04L9/06
CPC分类号： H04L63/0428 , G06F5/012 , G06F7/4876 , G06F7/724 , G06Q20/34 , G06Q20/401 , H03M7/00 , H04K3/25 , H04K3/827 , H04L9/0643
摘要： A first and a second device both have access to a series of data representing configurations of hash functions. The first device selects a first configuration and implements a hashing function from the selected configuration. A hash value is generated and transmitted to the second device. The second device has hashing configurations stored on a memory. A processor in the second device selects the first hashing configuration to implement the hash function from the first configuration and generates a hash value. The hash values generated on the first device and generated on the second device are compared to determine an action. The first configuration is disabled and a new configuration is retrieved. At least 4 and more preferably at least 5 different n-state functions with n>2 are used in a hash function.
摘要翻译：第一和第二设备都可以访问表示哈希函数的配置的一系列数据。第一个设备选择第一个配置，并从所选配置中实现散列函数。生成哈希值并将其传输到第二设备。第二个设备具有存储在存储器上的散列配置。第二设备中的处理器从第一配置中选择第一散列配置来实现散列函数并生成散列值。在第一设备上生成并在第二设备上生成的散列值被比较以确定动作。禁用第一个配置并检索新配置。在散列函数中使用至少4个，更优选至少5个具有n≥2的n状态函数。

7. 发明申请

US20160124717A1 Method and System of Improved Galois Multiplication 审中-公开
标题翻译：改进伽罗瓦乘法的方法和系统
公开(公告)号：US20160124717A1
公开(公告)日：2016-05-05
申请号：US14992918
申请日：2016-01-11
申请人： Echelon Corporation
发明人： Walter J. Downey
IPC分类号： G06F7/72 , G06F17/10 , H03M13/15
CPC分类号： G06F7/724 , G06F17/10 , G06F2207/72 , H03M13/1515
摘要： Embodiments of the invention include an apparatus for performing Galois multiplication using an enhanced Galois table. Galois multiplication may include converting a first and second multiplicand to exponential forms using a Galois table, adding the exponential forms of the first and second multiplicands, and converting the added exponential forms of the first and second multiplicands to a decimal equivalent binary form using the Galois table to decimal equivalent binary result of the Galois multiplication.
摘要翻译：本发明的实施例包括一种使用增强伽罗瓦表执行伽罗瓦乘法的装置。伽罗瓦乘法可以包括使用伽罗瓦表将第一和第二被乘数转换成指数形式，加上第一和第二被乘数的指数形式，并且使用伽罗瓦将第一和第二被乘数的相加指数形式转换为十进制等价二进制形式表格为十进制等值二进制结果的Galois乘法。

8. 发明授权

US09077536B2 Method and apparatus for solving discrete logarithm problem using pre-computation table 有权
标题翻译：使用预计算表解决离散对数问题的方法和装置
公开(公告)号：US09077536B2
公开(公告)日：2015-07-07
申请号：US13358674
申请日：2012-01-26
申请人： Jung Hee Cheon , Hyung Tae Lee , Jin Hong
发明人： Jung Hee Cheon , Hyung Tae Lee , Jin Hong
IPC分类号： G06F7/72 , H04L9/30
CPC分类号： H04L9/3013 , G06F7/724 , H04L2209/38
摘要： A method and apparatus for computing a discrete logarithm using a pre-computation table are provided. The method includes previously generating the pre-computation table consisting of chains of function values obtained by applying an iterating function to a predetermined number of initial values having a generator of the cyclic group as a base and having different exponents; and if a function value obtained by applying the iterating function to a value having a target element as a base and having an exponent is identical to a function value stored in the pre-computation table, computing the discrete logarithm of the target element by using exponent information of the two function values.
摘要翻译：提供了一种使用预计算表来计算离散对数的方法和装置。该方法包括以前生成的预计算表，其包括通过将迭代函数应用于具有循环组的生成器作为基础并具有不同指数的预定数量的初始值而获得的函数值链; 并且如果通过将迭代函数应用于具有目标元素作为基数并具有指数的值而获得的函数值与存储在预计算表中的函数值相同，则使用指数计算目标元素的离散对数两个函数值的信息。

9. 发明授权

US08943119B2 System and method to implement a matrix multiply unit of a broadband processor 有权
标题翻译：实现宽带处理器的矩阵乘法单元的系统和方法
公开(公告)号：US08943119B2
公开(公告)日：2015-01-27
申请号：US13462648
申请日：2012-05-02
申请人： Craig Hansen , Bruce Bateman , John Moussouris
发明人： Craig Hansen , Bruce Bateman , John Moussouris
IPC分类号： G06F7/38 , G06F7/52 , G06F7/533 , G06F7/57 , G06F7/72 , G06F9/30 , G06F17/15 , G06F17/16 , G06F7/48 , G06F7/499
CPC分类号： G06F7/5338 , G06F7/4812 , G06F7/49994 , G06F7/57 , G06F7/724 , G06F9/30014 , G06F9/30036 , G06F17/15 , G06F17/16 , G06F2207/3812 , G06F2207/382 , G06F2207/3824 , G06F2207/3828
摘要： A system and a method are configured to improve the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128 b by 128 b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
摘要翻译：一种系统和方法被配置为通过实现一个功能单元来提高通用处理器的性能，该功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。功能单元完全利用128b乘128b乘法器的整个资源，而不考虑操作数大小，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

10. 发明授权

US08898213B2 Apparatus and method for division of a Galois field binary polynomial 有权
标题翻译：用于划分伽罗瓦域二进制多项式的装置和方法
公开(公告)号：US08898213B2
公开(公告)日：2014-11-25
申请号：US13324322
申请日：2011-12-13
申请人： Ho Yang , Hyun Seok Lee , Ji Hoon Bang , Young Hwan Park , Ki Taek Bae , Kyeong Yeon Kim
发明人： Ho Yang , Hyun Seok Lee , Ji Hoon Bang , Young Hwan Park , Ki Taek Bae , Kyeong Yeon Kim
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： An apparatus and method for processing a division of a binary polynomial are provided. The apparatus includes a plurality of exclusive OR (XOR) operators that may perform a selective XOR operation with respect to a conditional bit of a dividend polynomial. The plurality of XOR operators may perform selective XOR operations in parallel and accordingly, a division of a binary polynomial may be rapidly performed.
摘要翻译：提供了一种用于处理二进制多项式的除法的装置和方法。该装置包括可以针对分红多项式的条件位执行选择性异或运算的多个异或（XOR）运算符。多个XOR运算符可以并行地执行选择性XOR运算，因此可以快速执行二进制多项式的除法。

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