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1. 发明申请

US20110007452A1 Lamellar Stacked Solid Electrolytic Capacitor 有权
标题翻译：层状堆叠固体电解电容器
公开(公告)号：US20110007452A1
公开(公告)日：2011-01-13
申请号：US12713398
申请日：2010-02-26
申请人： Ching-Feng Lin , Yui-Hsin Fran , Chi-Hao Chiu , Ming-Tsung Chen , Cheng-Wei Lai , Chun-Chia Huang
发明人： Ching-Feng Lin , Yui-Hsin Fran , Chi-Hao Chiu , Ming-Tsung Chen , Cheng-Wei Lai , Chun-Chia Huang
IPC分类号： H01G9/15
CPC分类号： H01G9/012 , H01G2/06 , H01G9/15
摘要： A lamellar stacked solid electrolytic capacitor includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit is composed of a negative foil, an isolation paper with conductive polymer substance, a positive foil, an isolation paper with conductive polymer substance and a negative foil that are stacked onto each other in sequence, the positive foils of the capacitor units are electrically connected to each other, the negative foils of the capacitor units are electrically connected to each other, and the positive foils and the negative foils are insulated from each other. The substrate unit has a positive guiding substrate electrically connected to the positive foils of the capacitor units and a negative guiding substrate electrically connected to the negative foils of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit.
摘要翻译：片状堆叠固体电解电容器包括多个电容器单元，基板单元和封装单元。每个电容器单元由负箔，具有导电聚合物物质的隔离纸，正箔，具有导电聚合物物质的隔离纸和负箔依次堆叠组成，电容器单元的正箔是彼此电连接，电容器单元的负箔彼此电连接，并且正箔和负箔彼此绝缘。基板单元具有电连接到电容器单元的正箔的正引导基板和电连接到电容器单元的负箔的负引导基板。封装单元覆盖电容器单元和衬底单元的一部分。

2. 发明授权

US08369066B2 Lamellar stacked solid electrolytic capacitor 有权
标题翻译：层状固体电解电容器
公开(公告)号：US08369066B2
公开(公告)日：2013-02-05
申请号：US12713398
申请日：2010-02-26
申请人： Ching-Feng Lin , Yui-Hsin Fran , Chi-Hao Chiu , Ming-Tsung Chen , Cheng-Wei Lai , Chun-Chia Huang
发明人： Ching-Feng Lin , Yui-Hsin Fran , Chi-Hao Chiu , Ming-Tsung Chen , Cheng-Wei Lai , Chun-Chia Huang
IPC分类号： H01G9/00
CPC分类号： H01G9/012 , H01G2/06 , H01G9/15
摘要： A lamellar stacked solid electrolytic capacitor includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit is composed of a negative foil, an isolation paper with conductive polymer substance, a positive foil, an isolation paper with conductive polymer substance and a negative foil that are stacked onto each other in sequence, the positive foils of the capacitor units are electrically connected to each other, the negative foils of the capacitor units are electrically connected to each other, and the positive foils and the negative foils are insulated from each other. The substrate unit has a positive guiding substrate electrically connected to the positive foils of the capacitor units and a negative guiding substrate electrically connected to the negative foils of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit.
摘要翻译：片状堆叠固体电解电容器包括多个电容器单元，基板单元和封装单元。每个电容器单元由负箔，具有导电聚合物物质的隔离纸，正箔，具有导电聚合物物质的隔离纸和负箔依次堆叠组成，电容器单元的正箔是彼此电连接，电容器单元的负箔彼此电连接，并且正箔和负箔彼此绝缘。基板单元具有电连接到电容器单元的正箔的正引导基板和电连接到电容器单元的负箔的负引导基板。封装单元覆盖电容器单元和衬底单元的一部分。

3. 发明授权

US08305734B2 Insulating encapsulation structure for solid chip electrolytic capacitor 有权
标题翻译：固体电解电容绝缘封装结构
公开(公告)号：US08305734B2
公开(公告)日：2012-11-06
申请号：US12907158
申请日：2010-10-19
申请人： Chi-Hao Chiu , Ming-Tsung Chen , Chiao-Yinms Yang
发明人： Chi-Hao Chiu , Ming-Tsung Chen , Chiao-Yinms Yang
IPC分类号： H01G9/08
CPC分类号： H01G9/15 , H01G9/08
摘要： An insulating encapsulation structure is applied to a chip type solid electrolytic capacitor that includes an aluminum metallic body having an aluminum core layer. An upper oxide film and a lower oxide film respectively having fine holes on their surfaces are respectively formed on the top and the bottom of the aluminum core layer. On side surfaces of the metallic body is a plurality of cut burrs. The upper oxide film and the lower oxide film of the metallic body are respectively separated by a separating layer to form an anode and a cathode. The insulating encapsulation structure includes an insulating cover layer enclosing an outer surface of the metallic body to cover the cut burrs. Thereby, the required chemical conversion process is reduced along with current leakage, the overall manufacturing cost is lowered, and the mechanical strength for the edge of the metallic body is reinforced.
摘要翻译：绝缘封装结构被应用于包括具有铝芯层的铝金属体的芯片型固体电解电容器。在铝芯层的顶部和底部分别形成表面上分别具有细孔的上氧化膜和低氧化膜。金属体的侧面是多个切割毛刺。金属体的上部氧化物膜和下部氧化物膜分别通过分离层分离以形成阳极和阴极。绝缘封装结构包括封闭金属体的外表面以覆盖切割毛刺的绝缘覆盖层。因此，随着电流泄漏，所需的化学转化过程减少，整体制造成本降低，并且增强了金属体边缘的机械强度。

4. 发明授权

US10608680B1 Dual mode communication device and dual mode communication module 有权
公开(公告)号：US10608680B1
公开(公告)日：2020-03-31
申请号：US16530555
申请日：2019-08-02
申请人： Ming-Tsung Chen
发明人： Ming-Tsung Chen
IPC分类号： H04W88/06 , H04B1/00
摘要： A dual mode communication device includes a control module, and a dual mode communication module. The dual mode communication module includes a first interface. The dual mode communication module is electrically connected to the control module through the first interface. The dual mode communication module includes a first communication unit, a second communication unit, a first antenna, and a second antenna. The first communication unit is electrically connected to the first interface. The second communication unit is electrically connected to the first communication unit. The first communication unit controls a turn-on state or a turn-off state of the second communication unit. The first antenna is electrically connected to the first communication unit of the dual mode communication module. The second antenna is electrically connected to the second communication unit of the dual mode communication module.

5. 发明授权

US09318571B2 Gate structure and method for trimming spacers 有权
标题翻译：用于修整间隔件的门结构和方法
公开(公告)号：US09318571B2
公开(公告)日：2016-04-19
申请号：US12391213
申请日：2009-02-23
申请人： I-Chang Wang , Ming-Tsung Chen , Ling-Chun Chou , Po-Chao Tsao , Tsung-Hung Chang , Hui-Ling Chen , Cheng-Yen Wu , Chieh-Te Chen , Shin-Chi Chen
发明人： I-Chang Wang , Ming-Tsung Chen , Ling-Chun Chou , Po-Chao Tsao , Tsung-Hung Chang , Hui-Ling Chen , Cheng-Yen Wu , Chieh-Te Chen , Shin-Chi Chen
IPC分类号： H01L21/64 , H01L29/49 , H01L29/66
CPC分类号： H01L29/4983 , H01L29/6653 , H01L29/6656
摘要： A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the first spacer and surrounding the gate, the second spacer is lower than the first spacer.
摘要翻译：栅极结构包括设置在衬底上的栅极，设置在衬底上并包围栅极的第一间隔物和设置在第一间隔物上并围绕栅极的第二间隔物，第二间隔物低于第一间隔物。

6. 发明申请

US20120300369A1 CONDUCTIVE STRUCTURE HAVING AN EMBEDDED ELECTRODE, AND SOLID CAPACITOR HAVING AN EMBEDDED ELECTRODE AND METHOD OF MAKING THE SAME 有权
标题翻译：具有嵌入电极的导电结构和具有嵌入电极的固体电容器及其制造方法
公开(公告)号：US20120300369A1
公开(公告)日：2012-11-29
申请号：US13115964
申请日：2011-05-25
申请人： WEI-CHIH LEE , Ming-Tsung Chen
发明人： WEI-CHIH LEE , Ming-Tsung Chen
IPC分类号： H01G4/06 , H01G7/00 , H01G9/15
CPC分类号： H01G9/012 , H01G9/052 , H01G9/15 , Y10T29/435
摘要： A solid capacitor having an embedded electrode includes a substrate unit, a first conductive unit, a second conductive unit, a first insulative unit, a third conductive unit, a second insulative unit, and an end electrode unit. The substrate unit includes a substrate body and a conductive body embedded into the substrate body. The substrate body has a lateral opening and a plurality of top openings, and the conductive body has a lateral conductive area exposed from the lateral opening and a plurality of top conductive areas respectively exposed from the top openings. The first conductive unit includes a plurality of first conductive layers respectively covering the top conductive areas. The second conductive unit includes a second conductive layer covering the first conductive layers. The porosity rate of the second conductive layer is larger than that of each first conductive layer.
摘要翻译：具有嵌入电极的固体电容器包括基板单元，第一导电单元，第二导电单元，第一绝缘单元，第三导电单元，第二绝缘单元和端电极单元。基板单元包括基板主体和嵌入基板主体中的导电体。基板主体具有侧向开口和多个顶部开口，并且导电体具有从侧向开口暴露的横向导电区域和分别从顶部开口露出的多个顶部导电区域。第一导电单元包括分别覆盖顶部导电区域的多个第一导电层。第二导电单元包括覆盖第一导电层的第二导电层。第二导电层的孔隙率大于每个第一导电层的孔隙率。

7. 发明授权

US08016012B2 Flattening mechanism for dry film laminator 有权
标题翻译：干膜层压机压平机构
公开(公告)号：US08016012B2
公开(公告)日：2011-09-13
申请号：US12699070
申请日：2010-02-03
申请人： Chin-Sen Lai , Ming-Tsung Chen
发明人： Chin-Sen Lai , Ming-Tsung Chen
IPC分类号： B32B37/00
CPC分类号： B32B43/00 , Y10T156/16
摘要： A flattening mechanism for dry film laminator includes a lower member connected to a dry film laminator. The lower member has a base portion formed thereon. The base portion has a plurality of air holes defined therein. The lower member has a lifting holder movably disposed thereon for holding a wafer. The wafer has a dry film disposed thereon. An upper member is movably disposed above the lower member. The upper member has a pressing portion disposed on a bottom thereof. The pressing portion has a steel plate disposed thereon and a first electric heating layer mounted on a top of the steel. A release film is movably guided between the upper member and the lower member, such that the wafer is lifted to press against the steel plate via the release film for enhancing a lamination of the dry film to the wafer and flattening the dry film.
摘要翻译：用于干膜层压机的压扁机构包括连接到干膜层压机的下部构件。下部构件具有形成在其上的基部。基部具有限定在其中的多个气孔。下部构件具有可移动地设置在其上用于保持晶片的提升保持器。晶片具有设置在其上的干膜。上部构件可移动地设置在下部构件的上方。上部构件具有设置在其底部的按压部。按压部具有设置在其上的钢板和安装在钢的顶部上的第一电加热层。剥离膜在上部构件和下部构件之间被可移动地引导，使得晶片被提升以经由隔离膜压靠钢板，用于增强干膜对晶片的层压并使干膜变平。

8. 发明授权

US07960838B2 Interconnect structure 有权
标题翻译：互连结构
公开(公告)号：US07960838B2
公开(公告)日：2011-06-14
申请号：US11164333
申请日：2005-11-18
申请人： Yu-Hao Hsu , Ming-Tsung Chen
发明人： Yu-Hao Hsu , Ming-Tsung Chen
IPC分类号： H01L23/48
CPC分类号： H01L21/76895 , H01L21/76807 , H01L21/76838 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a dielectric layer, a composite plug and a conductive line. The dielectric layer is disposed on the substrate covering the conductive part. The composite plug is disposed in the dielectric layer electrically connecting with the conductive part, and includes a first plug and a second plug on the first plug, wherein the material or the critical dimension of the second plug is different from that of the first plug. The conductive line is disposed on the dielectric layer electrically connecting with the composite plug.
摘要翻译：描述了一种互连结构，其设置在其上具有导电部分的基板上，并且包括电介质层，复合插塞和导电线。电介质层设置在覆盖导电部件的基板上。复合插头设置在与导电部件电连接的电介质层中，并且包括第一插头和第一插头上的第二插头，其中第二插头的材料或临界尺寸与第一插头的材料或临界尺寸不同。导电线设置在与复合插头电连接的电介质层上。

9. 发明申请

US20100327451A1 ALIGNMENT MARK 审中-公开
标题翻译：对齐标志
公开(公告)号：US20100327451A1
公开(公告)日：2010-12-30
申请号：US12878011
申请日：2010-09-08
申请人： Ling-Chun Chou , Ming-Tsung Chen , Hsi-Hua Liu , Shuen-Cheng Lei , Po-Chao Tsao
发明人： Ling-Chun Chou , Ming-Tsung Chen , Hsi-Hua Liu , Shuen-Cheng Lei , Po-Chao Tsao
IPC分类号： H01L23/498
CPC分类号： G03F7/70658 , G03F7/70633 , G03F7/7065 , G03F9/7076 , H01L22/12 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： An alignment mark for defect inspection is disclosed. The alignment mark includes: a semiconductor substrate; a first type well disposed in the semiconductor substrate; a second type doping region disposed in the first type well; a dielectric layer disposed on the semiconductor substrate to cover the first type well and the second type doping region; and a plurality of conductive plugs formed in the dielectric layer for connecting to the second type doping region.
摘要翻译：公开了一种用于缺陷检查的对准标记。对准标记包括：半导体衬底; 良好地设置在半导体衬底中的第一类型; 设置在第一类型阱中的第二类型掺杂区; 设置在所述半导体衬底上以覆盖所述第一类型阱和所述第二类型掺杂区的电介质层; 以及形成在所述电介质层中用于连接到所述第二类型掺杂区域的多个导电插塞。

10. 发明授权

US07825034B2 Method of fabricating openings and contact holes 有权
标题翻译：制造开口和接触孔的方法
公开(公告)号：US07825034B2
公开(公告)日：2010-11-02
申请号：US11163149
申请日：2005-10-06
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/76831
摘要： A substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer is then patterned to form a plurality of openings exposing the etch stop layer. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the etch stop layer. The dielectric thin film disposed on the dielectric layer and the etch stop layer is then removed.
摘要翻译：提供具有蚀刻停止层和至少从底部到顶部设置的电介质层的衬底。然后将电介质层图案化以形成露出蚀刻停止层的多个开口。随后形成介电薄膜以覆盖电介质层，开口的侧壁和蚀刻停止层。然后去除设置在电介质层和蚀刻停止层上的电介质薄膜。

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