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1. 发明申请

US20080001195A1 INTEGRATED CIRCUIT WITH HIGH VOLTAGE JUNCTION STRUCTURE 有权
标题翻译：具有高电压结构的集成电路
公开(公告)号：US20080001195A1
公开(公告)日：2008-01-03
申请号：US11426941
申请日：2006-06-28
申请人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
发明人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
IPC分类号： H01L29/94
CPC分类号： H01L27/092 , H01L21/823892
摘要： The high voltage integrated circuit comprises a P substrate. An N well barrier is disposed in the substrate. Separated P diffusion regions forming P wells are disposed in the substrate for serving as the isolation structures. The low voltage control circuit is located outside the N well barrier. A floating circuit is located inside the N well barrier. In order to develop a high voltage junction barrier in between the floating circuit and the substrate, the maximum space of devices of the floating circuit is restricted.
摘要翻译：高压集成电路包括P基板。在衬底中设置N阱势垒。形成P阱的分离的P扩散区域设置在基板中用作隔离结构。低压控制电路位于N阱屏障外。浮动电路位于N阱屏障内。为了在浮置电路和衬底之间形成高压结屏障，浮动电路的器件的最大空间受到限制。

2. 发明授权

US08125008B2 Schottky device and process of making the same comprising a geometry gap 有权
标题翻译：肖特基器件及其制造方法包括几何间隙
公开(公告)号：US08125008B2
公开(公告)日：2012-02-28
申请号：US11601131
申请日：2006-11-17
申请人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
发明人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
IPC分类号： H01L29/66
CPC分类号： H01L29/872 , H01L29/0692
摘要： A Schottky device and a semiconductor process of making the same are provided. The Schottky device comprises a substrate, a deep well, a Schottky contact, and an Ohmic contact. The substrate is doped with a first type of ions. The deep well is doped with a second type of ions, and formed in the substrate. The Schottky contact contacts a first electrode with the deep well. The Ohmic contact contacts a second electrode with a heavily doped region with the second type of ions in the deep well. Wherein the deep well has a geometry gap with a width formed under the Schottky contact, the first type of ions and the second type of ions are complementary, and the width of the gap adjusts the breakdown voltage.
摘要翻译：提供了一种肖特基器件及其制造方法。肖特基器件包括衬底，深阱，肖特基接触和欧姆接触。衬底掺杂有第一类型的离子。深阱掺杂有第二类离子，并形成在衬底中。肖特基接触器与深井接触第一电极。欧姆接触接触具有重掺杂区域的第二电极，第二种类型的离子在深阱中。其中深阱具有在肖特基接触下形成的宽度的几何间隙，第一类型的离子和第二类型的离子是互补的，并且间隙的宽度调节击穿电压。

3. 发明授权

US07732890B2 Integrated circuit with high voltage junction structure 有权
标题翻译：具有高压结结构的集成电路
公开(公告)号：US07732890B2
公开(公告)日：2010-06-08
申请号：US11426941
申请日：2006-06-28
申请人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
发明人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
IPC分类号： H01L29/00
CPC分类号： H01L27/092 , H01L21/823892
摘要： The high voltage integrated circuit comprises a P substrate. An N well barrier is disposed in the substrate. Separated P diffusion regions forming P wells are disposed in the substrate for serving as the isolation structures. The low voltage control circuit is located outside the N well barrier. A floating circuit is located inside the N well barrier. In order to develop a high voltage junction barrier in between the floating circuit and the substrate, the maximum space of devices of the floating circuit is restricted.
摘要翻译：高压集成电路包括P基片。在衬底中设置N阱势垒。形成P阱的分离的P扩散区域设置在基板中用作隔离结构。低压控制电路位于N阱屏障外。浮动电路位于N阱屏障内。为了在浮置电路和衬底之间形成高压结屏障，浮动电路的器件的最大空间受到限制。

4. 发明授权

US07655990B2 Voltage-clipping device with high breakdown voltage 有权
标题翻译：具有高击穿电压的钳位装置
公开(公告)号：US07655990B2
公开(公告)日：2010-02-02
申请号：US11424530
申请日：2006-06-15
申请人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
发明人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
IPC分类号： H01L29/94
CPC分类号： H01L29/808
摘要： The present invention proposes a voltage-clipping device utilizing a pinch-off mechanism formed by two depletion boundaries. A clipping voltage of the voltage-clipping device can be adjusted in response to a gate voltage; a gap of a quasi-linked well; and a doping concentration and a depth of the quasi-linked well and a well with complementary doping polarity to the quasi-linked well. The voltage-clipping device can be integrated within a semiconductor device as a voltage stepping down device in a tiny size, compared to traditional transformers.
摘要翻译：本发明提出了利用由两个耗尽边界形成的夹断机构的电压剪切装置。可以响应于栅极电压来调节电压限幅装置的限幅电压; 准连接井的缺口; 以及准连接阱的掺杂浓度和深度以及与准连接阱具有互补掺杂极性的阱。与传统的变压器相比，电压钳位装置可以与微型尺寸的电压降压装置集成在半导体器件内。

5. 发明申请

US20080116539A1 Schottky device and process of making the same 有权
标题翻译：肖特基器件和制作过程相同
公开(公告)号：US20080116539A1
公开(公告)日：2008-05-22
申请号：US11601131
申请日：2006-11-17
申请人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
发明人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L29/0692
摘要： A Schottky device and a semiconductor process of making the same are provided. The Schottky device comprises a substrate, a deep well, a Schottky contact, and an Ohmic contact. The substrate is doped with a first type of ions. The deep well is doped with a second type of ions, and formed in the substrate. The Schottky contact contacts a first electrode with the deep well. The Ohmic contact contacts a second electrode with a heavily doped region with the second type of ions in the deep well. Wherein the deep well has a geometry gap with a width formed under the Schottky contact, the first type of ions and the second type of ions are complementary, and the width of the gap adjusts the breakdown voltage. In addition, the semiconductor process comprises the steps of forming a deep well with a second type of ions in a substrate with a first type of ions; forming a first doped region with the first type of ions; forming an oxide layer; forming a second doped region in the deep well with the first type of ions; forming a heavily doped region in the deep well with the second type of ions; and forming a first electrode on a Schottky contact on the deep well and a second electrode on an Ohmic contact on the heavily doped region.
摘要翻译：提供了一种肖特基器件及其制造方法。肖特基器件包括衬底，深阱，肖特基接触和欧姆接触。衬底掺杂有第一类型的离子。深阱掺杂有第二类离子，并形成在衬底中。肖特基接触器与深井接触第一电极。欧姆接触接触具有重掺杂区域的第二电极，第二种类型的离子在深阱中。其中深阱具有在肖特基接触下形成的宽度的几何间隙，第一类型的离子和第二类型的离子是互补的，并且间隙的宽度调节击穿电压。此外，半导体工艺包括以下步骤：在具有第一类型离子的衬底中形成具有第二类型离子的深阱; 形成具有所述第一类型离子的第一掺杂区域; 形成氧化物层; 在所述深井中用所述第一类型的离子形成第二掺杂区域; 在深井中用第二类离子形成重掺杂区; 以及在深阱上的肖特基接触上形成第一电极，在重掺杂区域上的欧姆接触上形成第二电极。

6. 发明申请

US20070290276A1 VOLTAGE-CLIPPING DEVICE WITH HIGH BREAKDOWN VOLTAGE 有权
标题翻译：具有高断路电压的电压切断装置
公开(公告)号：US20070290276A1
公开(公告)日：2007-12-20
申请号：US11424530
申请日：2006-06-15
申请人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
发明人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
IPC分类号： H01L29/94
CPC分类号： H01L29/808
摘要： The present invention proposes a voltage-clipping device utilizing a pinch-off mechanism formed by two depletion boundaries. A clipping voltage of the voltage-clipping device can be adjusted in response to a gate voltage; a gap of a quasi-linked well; and a doping concentration and a depth of the quasi-linked well and a well with complementary doping polarity to the quasi-linked well. The voltage-clipping device can be integrated within a semiconductor device as a voltage stepping down device in a tiny size, compared to traditional transformers.
摘要翻译：本发明提出了利用由两个耗尽边界形成的夹断机构的电压剪切装置。可以响应于栅极电压来调节电压限幅装置的限幅电压; 准连接井的缺口; 以及准连接阱的掺杂浓度和深度以及与准连接阱具有互补掺杂极性的阱。与传统的变压器相比，电压钳位装置可以与微型尺寸的电压降压装置集成在半导体器件内。

7. 发明申请

US20070247225A1 Switching circuit of power converter having voltage-clipping device to improve efficiency 有权
标题翻译：具有电压钳位装置的功率转换器的开关电路，以提高效率
公开(公告)号：US20070247225A1
公开(公告)日：2007-10-25
申请号：US11407537
申请日：2006-04-19
申请人： Chih-Feng Huang , Chiu-Chih Chiang , You-Kuo Wu , Wei-Hsuan Huang , Ta-yung Yang
发明人： Chih-Feng Huang , Chiu-Chih Chiang , You-Kuo Wu , Wei-Hsuan Huang , Ta-yung Yang
IPC分类号： H03F1/36
CPC分类号： H02M1/36 , H02M2001/0006
摘要： A switching circuit for power converters is presented. It includes a voltage-clipping device, a resistive device, a first transistor and a second transistor. The voltage-clipping device is coupled to an input voltage. The first transistor is connected in series with the voltage-clipping device for switching the input voltage. The second transistor is coupled to control the first transistor and the voltage-clipping device in response to a control signal. The resistive device provides a bias voltage to turn on the voltage-clipping device and the first transistor when the second transistor is turned off. Once the second transistor is turned on, the first transistor is turned off and the voltage-clipping device is negatively biased. The voltage-clipping device is developed to clamp a maximum voltage for the first transistor.
摘要翻译：提出了一种电源转换器的开关电路。它包括电压限幅装置，电阻装置，第一晶体管和第二晶体管。电压限幅装置耦合到输入电压。第一晶体管与用于切换输入电压的电压限幅装置串联连接。第二晶体管被耦合以响应于控制信号来控制第一晶体管和电压限幅装置。当第二晶体管截止时，电阻器件提供偏置电压以接通压限器件和第一晶体管。一旦第二晶体管导通，第一晶体管被截止并且电压限幅器件被负偏置。钳位装置被开发以钳位第一晶体管的最大电压。

8. 发明授权

US07615976B2 Switching circuit of power converter having voltage-clipping device to improve efficiency 有权
标题翻译：具有电压钳位装置的功率转换器的开关电路，以提高效率
公开(公告)号：US07615976B2
公开(公告)日：2009-11-10
申请号：US11407537
申请日：2006-04-19
申请人： Chih-Feng Huang , Chiu-Chih Chiang , You-Kuo Wu , Wei-Hsuan Huang , Ta-yung Yang
发明人： Chih-Feng Huang , Chiu-Chih Chiang , You-Kuo Wu , Wei-Hsuan Huang , Ta-yung Yang
IPC分类号： G05F1/00
CPC分类号： H02M1/36 , H02M2001/0006
摘要： A switching circuit for power converters is presented. It includes a voltage-clipping device, a resistive device, a first transistor and a second transistor. The voltage-clipping device is coupled to an input voltage. The first transistor is connected in series with the voltage-clipping device for switching the input voltage. The second transistor is coupled to control the first transistor and the voltage-clipping device in response to a control signal. The resistive device provides a bias voltage to turn on the voltage-clipping device and the first transistor when the second transistor is turned off. Once the second transistor is turned on, the first transistor is turned off and the voltage-clipping device is negatively biased. The voltage-clipping device is developed to clamp a maximum voltage for the first transistor.
摘要翻译：提出了一种电源转换器的开关电路。它包括电压限幅装置，电阻装置，第一晶体管和第二晶体管。电压限幅装置耦合到输入电压。第一晶体管与用于切换输入电压的电压限幅装置串联连接。第二晶体管被耦合以响应于控制信号来控制第一晶体管和电压限幅装置。当第二晶体管截止时，电阻器件提供偏置电压以接通压限器件和第一晶体管。一旦第二晶体管导通，第一晶体管被截止并且电压限幅器件被负偏置。钳位装置被开发以钳位第一晶体管的最大电压。

9. 发明申请

US20120217657A1 MULTI-CHIP MODULE PACKAGE 审中-公开
标题翻译：多芯片模块包装
公开(公告)号：US20120217657A1
公开(公告)日：2012-08-30
申请号：US13468862
申请日：2012-05-10
申请人： Chih-Feng Huang , Chiu-Chih Chiang , You-Kuo Wu , Lih-Ming Doong
发明人： Chih-Feng Huang , Chiu-Chih Chiang , You-Kuo Wu , Lih-Ming Doong
IPC分类号： H01L23/488
CPC分类号： H01L25/18 , H01L23/3107 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L25/072 , H01L25/074 , H01L2224/05639 , H01L2224/29101 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48247 , H01L2224/484 , H01L2224/48599 , H01L2224/73265 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/0781 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the first chip carrier, wherein the second conductive adhesive is made of an adhesive material the same as that of the first conductive material, a plurality of conductive elements to electrically connect the first chip to the second chip and an encapsulant encapsulating the first chip, the first chip carrier, the second chip, the second chip carrier and the plurality of conductive elements, allowing a portion of both chip carriers to be exposed to the encapsulant, so that the first chip and second chip are able to be insulated by the separation of the first and second chip carriers.
摘要翻译：提供了一种多芯片模块封装，其包括经由第一导电粘合剂安装并电连接到第一芯片载体的第一芯片，经由第二导电粘合剂安装的第二芯片，并电连接到第二芯片载体，第二芯片载体是与第一芯片载体间隔开，其中第二导电粘合剂由与第一导电材料相同的粘合剂材料制成，多个导电元件将第一芯片电连接到第二芯片，以及密封剂封装第一芯片芯片，第一芯片载体，第二芯片，第二芯片载体和多个导电元件，允许两个芯片载体的一部分暴露于密封剂，使得第一芯片和第二芯片能够由分离第一和第二芯片载体。

10. 发明申请

US20090051019A1 Multi-chip module package 审中-公开
标题翻译：多芯片模块封装
公开(公告)号：US20090051019A1
公开(公告)日：2009-02-26
申请号：US11894341
申请日：2007-08-20
申请人： Chih-Feng Huang , Chiu-Chih Chiang , You-Kuo Wu , Lih-Ming Doong
发明人： Chih-Feng Huang , Chiu-Chih Chiang , You-Kuo Wu , Lih-Ming Doong
IPC分类号： H01L23/495 , H01L23/02
CPC分类号： H01L25/18 , H01L23/3107 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L25/072 , H01L25/074 , H01L2224/05639 , H01L2224/29101 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48247 , H01L2224/484 , H01L2224/48599 , H01L2224/73265 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/0781 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the first chip carrier, wherein the second conductive adhesive is made of an adhesive material the same as that of the first conductive material, a plurality of conductive elements to electrically connect the first chip to the second chip and an encapsulant encapsulating the first chip, the first chip carrier, the second chip, the second chip carrier and the plurality of conductive elements, allowing a portion of both chip carriers to be exposed to the encapsulant, so that the first chip and second chip are able to be insulated by the separation of the first and second chip carriers.
摘要翻译：提供了一种多芯片模块封装，其包括经由第一导电粘合剂安装并电连接到第一芯片载体的第一芯片，经由第二导电粘合剂安装的第二芯片，并电连接到第二芯片载体，第二芯片载体是与第一芯片载体间隔开，其中第二导电粘合剂由与第一导电材料相同的粘合剂材料制成，多个导电元件将第一芯片电连接到第二芯片，以及密封剂封装第一芯片芯片，第一芯片载体，第二芯片，第二芯片载体和多个导电元件，允许两个芯片载体的一部分暴露于密封剂，使得第一芯片和第二芯片能够被分离第一和第二芯片载体。

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