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1. 发明申请

US20080068913A1 REFRESHING THE CONTENT OF A MEMORY CELL OF A MEMORY ARRANGEMENT 失效
标题翻译：刷新内存安排的内存单元的内容
公开(公告)号：US20080068913A1
公开(公告)日：2008-03-20
申请号：US11856621
申请日：2007-09-17
申请人： Christian Sichert , Paul Wallner
发明人： Christian Sichert , Paul Wallner
IPC分类号： G11C7/00
CPC分类号： G11C11/406
摘要： A method of refreshing the content of a memory cell of a memory arrangement includes selectively controlling a refreshing device of the memory arrangement via an interface of the memory arrangement or by an internal control device of the memory arrangement to refresh the content of the memory arrangement.
摘要翻译：刷新存储器装置的存储单元的内容的方法包括经由存储器装置的接口或存储器装置的内部控制装置选择性地控制存储器装置的刷新装置，以刷新存储器装置的内容。

2. 发明授权

US07334150B2 Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals 有权
标题翻译：具有时钟信号再生电路的存储器模块和用于临时存储输入命令和地址信号的寄存器电路
公开(公告)号：US07334150B2
公开(公告)日：2008-02-19
申请号：US11002148
申请日：2004-12-03
申请人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G06F1/04
CPC分类号： G11C5/04 , G11C5/063
摘要： A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.
摘要翻译：半导体存储器模块包括多个半导体存储器芯片和总线信号线，其向半导体存储器芯片提供输入时钟信号和输入命令和地址信号。时钟信号再生电路和寄存器电路以连接到总线信号线的公共芯片封装布置在半导体存储器模块中。时钟信号再生电路和寄存器电路分别对输入的时钟信号进行调节，并临时存储输入的命令和地址信号，分别将经调节的时钟信号和临时存储的命令和地址信号乘以1：X，分别提供对半导体存储器芯片调节时钟信号和临时存储的命令和地址信号。

3. 发明申请

US20060104132A1 SEMICONDUCTOR MEMORY SYSTEM AND METHOD FOR THE TRANSFER OF WRITE AND READ DATA SIGNALS IN A SEMICONDUCTOR MEMORY SYSTEM 有权
标题翻译：用于半导体存储器系统中写入和读取数据信号的半导体存储器系统和方法
公开(公告)号：US20060104132A1
公开(公告)日：2006-05-18
申请号：US10986767
申请日：2004-11-15
申请人： Hermann Ruckerbauer , Dominique Savignac , Christian Sichert , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Dominique Savignac , Christian Sichert , Peter Gregorius , Paul Wallner
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/1018
摘要： A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.
摘要翻译：用于在接口电路之间传送写入和读取数据信号的半导体存储器系统包括至少一个存储器件，存储器控制器单元和可选地半导体存储器系统的寄存器单元，其中数据信号各自以信号脉冲串具体的突发长度。该系统的特征在于，延伸突发长度的多个附加位与至少每个第n个信号脉冲串一起传送。

4. 发明授权

US07221615B2 Semiconductor memory chip 有权
标题翻译：半导体存储芯片
公开(公告)号：US07221615B2
公开(公告)日：2007-05-22
申请号：US11242150
申请日：2005-10-04
申请人： Paul Wallner , Martin Streibl , Manfred Menke , Yukio Fukuzo , Christian Sichert , Peter Gregorius
发明人： Paul Wallner , Martin Streibl , Manfred Menke , Yukio Fukuzo , Christian Sichert , Peter Gregorius
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1006 , G11C11/4096
摘要： A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.
摘要翻译：半导体存储器芯片包括：接收接口部分，用于以串行信号帧的形式接收外部数据，命令和地址信号; 中间数据缓冲器，用于中间存储写入数据，以及可选地写入要写入存储单元阵列的数据屏蔽位; 具有存储体组织的存储单元阵列的存储器核心; 解码器部分，用于对从接收接口部分接收的信号帧导出的地址进行解码，用于根据在一个或多个接收信号中的写入/读取命令向/从存储器单元阵列的一个或多个存储器组写入/读取数据框架以及帧解码器，被设置为在接收接口部分和存储器核心之间的接口，用于解码包括在一个或多个帧中的一个或多个命令，并将数据地址，命令和读/写访问指示信号输出到存储器核心中间数据缓冲区。

5. 发明申请

US20070076004A1 Semiconductor memory chip 失效
标题翻译：半导体存储芯片
公开(公告)号：US20070076004A1
公开(公告)日：2007-04-05
申请号：US11242149
申请日：2005-10-04
申请人： Paul Wallner , Yukio Fukuzo , Christian Sichert , Paul Schmolz
发明人： Paul Wallner , Yukio Fukuzo , Christian Sichert , Paul Schmolz
IPC分类号： G06T1/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/109 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a reception interface. The frame decoder includes a command type decoder for decoding the types of commands included in frames according to the decoded type of the commands, a memory command evaluator/generator for scheduling and preparing single commands for the core, an intermediate data buffer command evaluator/generator for scheduling and preparing control signals for an intermediate data buffer, and a system command evaluator/generator for preparing and scheduling system commands. These system commands provide timing parameters to ensure time intervals between consecutive commands within one frame or between frames and are stored in a system mode register. The operation of the frame decoder is edge-synchronized by a frame clock or a synchronization decoder clock signal which is phase-aligned to that frame clock signal.
摘要翻译：信号作为串行信号帧传送的半导体存储器芯片包括提供存储器核心和接收接口之间的接口的帧解码器。帧解码器包括用于根据解码的命令类型对包括在帧中的命令的类型进行解码的命令类型解码器，用于调度和准备用于核心的单个命令的存储器命令评估器/生成器，中间数据缓冲器命令评估器/生成器用于调度和准备中间数据缓冲器的控制信号，以及用于准备和调度系统命令的系统命令评估器/发生器。这些系统命令提供定时参数，以确保一帧内或帧之间的连续命令之间的时间间隔，并存储在系统模式寄存器中。帧解码器的操作由帧时钟或同步解码器时钟信号进行边沿同步，该时钟信号与该帧时钟信号相对齐。

6. 发明申请

US20070061671A1 Data memory system and method for transferring data into a data memory 有权
标题翻译：用于将数据传送到数据存储器的数据存储器系统和方法
公开(公告)号：US20070061671A1
公开(公告)日：2007-03-15
申请号：US11217081
申请日：2005-08-30
申请人： Paul Wallner , Dominique Savignac , Christian Sichert , Thomas Hein
发明人： Paul Wallner , Dominique Savignac , Christian Sichert , Thomas Hein
IPC分类号： H03M13/00
CPC分类号： G06F13/4243 , G06F11/1052
摘要： A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.
摘要翻译：提出了一种使用数据协议将数据传输到数据存储器中的方法。数据存储器是纠错码（ECC）存储器或非纠错码存储器。数据协议具有不同的帧。当数据被写入ECC存储器时，该协议包括数据屏蔽帧，其中数据屏蔽位被ECC位替换。该方法被设计成使得可以使用相同的协议和至少相似的架构来建立ECC和非ECC DRAM。

7. 发明授权

US07173877B2 Memory system with two clock lines and a memory device 有权
标题翻译：具有两个时钟线和存储器件的存储器系统
公开(公告)号：US07173877B2
公开(公告)日：2007-02-06
申请号：US10955177
申请日：2004-09-30
申请人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/063 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.
摘要翻译：本发明涉及一种具有两条时钟线的存储器件的存储器系统。本发明的一个实施例提供了一种存储器系统，其包括至少一个存储器件，用于控制存储器件的操作的存储器控制器，从存储器控制器的写时钟输出延伸到存储器的时钟端口的第一时钟线向存储器件提供时钟信号的第二时钟线，以及从存储器件的时钟端口延伸到存储器控制器的读时钟输入端的第二时钟线，以将施加到存储器件的时钟端口的时钟信号转发回到存储器控制器的读时钟输入。存储器件还可以包括同步电路，其适于从存储器控制器接收时钟信号，并提供与转发的时钟信号同步的输出数据。

8. 发明授权

US07050340B1 Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system 有权
标题翻译：半导体存储器系统和用于在半导体存储器系统中传送写和读数据信号的方法
公开(公告)号：US07050340B1
公开(公告)日：2006-05-23
申请号：US10986767
申请日：2004-11-15
申请人： Hermann Ruckerbauer , Dominique Savignac , Christian Sichert , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Dominique Savignac , Christian Sichert , Peter Gregorius , Paul Wallner
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/1018
摘要： A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.
摘要翻译：用于在接口电路之间传送写入和读取数据信号的半导体存储器系统包括至少一个存储器件，存储器控制器单元和可选地半导体存储器系统的寄存器单元，其中数据信号各自以信号脉冲串具体的突发长度。该系统的特征在于，延伸突发长度的多个附加位与至少每个第n个信号脉冲串一起传送。

9. 发明授权

US07733732B2 Refreshing the content of a memory cell of a memory arrangement 失效
标题翻译：刷新存储器装置的存储单元的内容
公开(公告)号：US07733732B2
公开(公告)日：2010-06-08
申请号：US11856621
申请日：2007-09-17
申请人： Christian Sichert , Paul Wallner
发明人： Christian Sichert , Paul Wallner
IPC分类号： G11C7/00
CPC分类号： G11C11/406
摘要： A method of refreshing the content of a memory cell of a memory arrangement includes selectively controlling a refreshing device of the memory arrangement via an interface of the memory arrangement or by an internal control device of the memory arrangement to refresh the content of the memory arrangement.
摘要翻译：刷新存储器装置的存储单元的内容的方法包括经由存储器装置的接口或存储器装置的内部控制装置选择性地控制存储器装置的刷新装置，以刷新存储器装置的内容。

10. 发明授权

US07428689B2 Data memory system and method for transferring data into a data memory 有权
标题翻译：用于将数据传送到数据存储器的数据存储器系统和方法
公开(公告)号：US07428689B2
公开(公告)日：2008-09-23
申请号：US11217081
申请日：2005-08-30
申请人： Paul Wallner , Dominique Savignac , Christian Sichert , Thomas Hein
发明人： Paul Wallner , Dominique Savignac , Christian Sichert , Thomas Hein
IPC分类号： G06F11/10
CPC分类号： G06F13/4243 , G06F11/1052
摘要： A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.
摘要翻译：提出了一种使用数据协议将数据传输到数据存储器中的方法。数据存储器是纠错码（ECC）存储器或非纠错码存储器。数据协议具有不同的帧。当数据被写入ECC存储器时，该协议包括数据屏蔽帧，其中数据屏蔽位被ECC位替换。该方法被设计成使得可以使用相同的协议和至少相似的架构来建立ECC和非ECC DRAM。

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