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1. 发明申请

US20090217115A1 Method for Optimizing Scan Chains in an Integrated Circuit that has Multiple Levels of Hierarchy 有权
标题翻译：用于优化具有多层次结构的集成电路中的扫描链的方法
公开(公告)号：US20090217115A1
公开(公告)日：2009-08-27
申请号：US12035500
申请日：2008-02-22
申请人： Christopher J. Berry , Lawrence David Curley , Patrick James Meaney , Diana Lynn Orf
发明人： Christopher J. Berry , Lawrence David Curley , Patrick James Meaney , Diana Lynn Orf
IPC分类号： G01R31/3181
CPC分类号： G01R31/318536
摘要： A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.
摘要翻译：一种用于优化集成电路中具有多层次层次结构的扫描链的方法，可以解决无限链和树桩，并分开所有其他链和树桩。通过将链包围的区域和残端的起始点和终点分成由多个网格框组成的网格，并且将网格框确定为网格框连接路由以访问所有网格框，来优化无限链和树桩的起始点和终点之间的网格框通过运行路由算法的计算机。优化的所有其他链和树桩被随机地分配给一个树桩，一个可以通过该树桩物理达到的链，并根据附加链中的锁存数，其物理位置和锁存数量向该残基添加一个附加链已分配

2. 发明授权

US07987400B2 Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy 有权
标题翻译：优化具有多层次结构的集成电路中的扫描链的方法
公开(公告)号：US07987400B2
公开(公告)日：2011-07-26
申请号：US12035500
申请日：2008-02-22
申请人： Christopher J. Berry , Lawrence David Curley , Patrick James Meaney , Diana Lynn Orf
发明人： Christopher J. Berry , Lawrence David Curley , Patrick James Meaney , Diana Lynn Orf
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/318536
摘要： A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.
摘要翻译：一种用于优化集成电路中具有多层次层次结构的扫描链的方法，可以解决无限链和树桩，并分开所有其他链和树桩。通过将链包围的区域和残端的起始点和终点分成由多个网格框组成的网格，并且将网格框确定为网格框连接路由以访问所有网格框，来优化无限链和树桩的起始点和终点之间的网格框通过运行路由算法的计算机。优化的所有其他链和树桩被随机地分配给一个树桩，一个可以通过该树桩物理达到的链，并根据附加链中的锁存数，其物理位置和锁存数量向该残基添加一个附加链已分配

3. 发明申请

US20110320855A1 ERROR DETECTION AND RECOVERY IN A SHARED PIPELINE 失效
标题翻译：在共享管道中的错误检测和恢复
公开(公告)号：US20110320855A1
公开(公告)日：2011-12-29
申请号：US12821871
申请日：2010-06-23
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F11/07
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/0793
摘要： A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.
摘要翻译：流水线处理装置包括：被配置为接收执行操作的请求的处理器; 多个处理控制器，被配置为接收与所述操作相关联的至少一个指令，所述多个处理控制器中的每个处理控制器包括用于在其中存储至少一个指令的存储器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器包括被配置为在流水线中处理所述至少一个指令时检测所述至少一个指令中的奇偶校验错误的共享错误检测逻辑，并且生成错误信号 ; 以及连接到所述多个处理控制器中的每个处理控制器并被配置为传送来自所述错误检测逻辑的所述错误信号的流水线总线。

4. 发明申请

US20110314183A1 SYSTEM AND METHOD FOR MANAGING DATAFLOW IN A TEMPORARY MEMORY 失效
标题翻译：用于管理临时存储器中的数据流的系统和方法
公开(公告)号：US20110314183A1
公开(公告)日：2011-12-22
申请号：US12820589
申请日：2010-06-22
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F3/00 , G06F5/14
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/073 , G06F12/0897 , Y02D10/13
摘要： A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.
摘要翻译：管理临时存储器的方法包括：接收从源位置传送数据到目的地位置的请求，与要执行的操作相关联的数据传输请求，从输入中选择的中间临时存储器和输出 ; 检查与临时存储器相关联的两状态指示符，两状态指示符具有指示临时存储器上的紧接在前的操作是临时存储器的输入的第一状态，以及指示紧接在前的操作是第二状态的第二状态从临时存储器输出; 并且响应于以下操作中的一个执行操作：作为输入操作的操作和处于第二状态的两状态指示器，指示紧接在前的操作是输出; 操作是输出操作，两状态指示灯处于第一状态，表示紧接在前的操作是输入。

5. 发明申请

US20110320863A1 DYNAMIC RE-ALLOCATION OF CACHE BUFFER SLOTS 审中-公开
标题翻译：缓存缓冲区的动态重新分配
公开(公告)号：US20110320863A1
公开(公告)日：2011-12-29
申请号：US12822407
申请日：2010-06-24
申请人： Ekaterina M. Amroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Amroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F11/20 , G06F12/08 , G06F11/00
CPC分类号： G06F12/126 , G06F11/0724 , G06F11/073 , G06F11/0793 , G06F11/1666 , G06F11/20 , G06F12/0802 , G06F2212/1032
摘要： Dynamic re-allocation of cache buffer slots includes moving data out of a reserved buffer slot upon detecting an error in the reserved buffer slot, creating a new buffer slot, and storing the data moved out of the reserved buffer slot in the new buffer slot.
摘要翻译：高速缓冲存储器时隙的动态重新分配包括在检测到保留的缓冲器时隙中的错误时产生保留的缓冲器时隙中的数据，创建新的缓冲时隙，以及将保留的缓冲时隙中移出的数据存储在新的缓冲时隙中。

6. 发明申请

US20110320731A1 ON DEMAND ALLOCATION OF CACHE BUFFER SLOTS 有权
标题翻译：关于缓存缓冲区的需求分配
公开(公告)号：US20110320731A1
公开(公告)日：2011-12-29
申请号：US12822398
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Diana Lynn Orf
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Diana Lynn Orf
IPC分类号： G06F12/08 , G06F13/00 , G06F3/00
CPC分类号： G06F12/0895 , G06F12/0871
摘要： Dynamic allocation of cache buffer slots includes receiving a request to perform an operation that requires a storage buffer slot, the storage buffer slot residing in a level of storage. The dynamic allocation of cache buffer slots also includes determining availability of the storage buffer slot for the cache index as specified by the request. Upon determining the storage buffer slot is not available, the dynamic allocation of cache buffer slots includes evicting data stored in the storage buffer slot, and reserving the storage buffer slot for data associated with the request.
摘要翻译：高速缓存缓存槽的动态分配包括接收执行需要存储缓冲器时隙的操作的请求，存储缓冲槽位于存储级别。高速缓存缓存槽的动态分配还包括确定请求指定的高速缓存索引的存储缓冲区的可用性。在确定存储缓冲器时隙不可用时，高速缓存缓冲器时隙的动态分配包括驱逐存储在存储缓冲器时隙中的数据，并且为与请求相关联的数据保留存储缓冲器时隙。

7. 发明授权

US09104583B2 On demand allocation of cache buffer slots 有权
标题翻译：缓存缓存槽的按需分配
公开(公告)号：US09104583B2
公开(公告)日：2015-08-11
申请号：US12822398
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Diana Lynn Orf
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Diana Lynn Orf
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0871
摘要： Dynamic allocation of cache buffer slots includes receiving a request to perform an operation that requires a storage buffer slot, the storage buffer slot residing in a level of storage. The dynamic allocation of cache buffer slots also includes determining availability of the storage buffer slot for the cache index as specified by the request. Upon determining the storage buffer slot is not available, the dynamic allocation of cache buffer slots includes evicting data stored in the storage buffer slot, and reserving the storage buffer slot for data associated with the request.
摘要翻译：高速缓存缓存槽的动态分配包括接收执行需要存储缓冲器时隙的操作的请求，存储缓冲槽位于存储级别。高速缓存缓存槽的动态分配还包括确定请求指定的高速缓存索引的存储缓冲区的可用性。在确定存储缓冲器时隙不可用时，高速缓存缓冲器时隙的动态分配包括驱逐存储在存储缓冲器时隙中的数据，并且为与请求相关联的数据保留存储缓冲器时隙。

8. 发明授权

US08671267B2 Monitoring processing time in a shared pipeline 失效
标题翻译：在共享管道中监视处理时间
公开(公告)号：US08671267B2
公开(公告)日：2014-03-11
申请号：US12822359
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F9/30 , G06F9/40 , G06F13/00 , G06F3/00
CPC分类号： G06F9/3867 , G06F11/3419 , G06F11/3466 , G06F2201/88
摘要： A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at least a portion of a time taken to process the at least one instruction; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor configured to receive the active time value; and a shared pipeline storage area configured to store the active time value for each of the plurality of subcontrollers.
摘要翻译：流水线处理装置包括：设备控制器，被配置为接收执行操作的请求; 多个子控制器被配置为接收与所述操作相关联的至少一个指令，所述多个子控制器中的每一个包括配置成生成指示处理所述至少一个指令所花费的时间的至少一部分的活动时间值的计数器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器被配置为接收所述活动时间值; 以及共享流水线存储区域，被配置为存储多个子控制器中的每一个的活动时间值。

9. 发明授权

US08522076B2 Error detection and recovery in a shared pipeline 失效
标题翻译：共享管道中的错误检测和恢复
公开(公告)号：US08522076B2
公开(公告)日：2013-08-27
申请号：US12821871
申请日：2010-06-23
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F11/00
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/0793
摘要： A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.
摘要翻译：流水线处理装置包括：被配置为接收执行操作的请求的处理器; 多个处理控制器，被配置为接收与所述操作相关联的至少一个指令，所述多个处理控制器中的每个处理控制器包括用于在其中存储至少一个指令的存储器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器包括被配置为在流水线中处理所述至少一个指令时检测所述至少一个指令中的奇偶校验错误的共享错误检测逻辑，并且生成错误信号 ; 以及连接到所述多个处理控制器中的每个处理控制器并被配置为传送来自所述错误检测逻辑的所述错误信号的流水线总线。

10. 发明授权

US08468536B2 Multiple level linked LRU priority 失效
标题翻译：多级链接LRU优先级
公开(公告)号：US08468536B2
公开(公告)日：2013-06-18
申请号：US12822514
申请日：2010-06-24
申请人： Deanna Postles Dunn Berger , Ekaterina M. Ambroladze , Michael Fee , Diana Lynn Orf
发明人： Deanna Postles Dunn Berger , Ekaterina M. Ambroladze , Michael Fee , Diana Lynn Orf
IPC分类号： G06F9/46 , G06F13/00 , G06F13/38
CPC分类号： G06F13/14
摘要： A method that includes providing LRU selection logic which controllably pass requests for access to computer system resources to a shared resource via a first level and a second level, determining whether a request in a request group is active, presenting the request to LRU selection logic at the first level, when it is determined that the request is active, determining whether the request is a LRU request of the request group at the first level, forwarding the request to the second level when it is determined that the request is the LRU request of the request group, comparing the request to an LRU request from each of the request groups at the second level to determine whether the request is a LRU request of the plurality of request groups, and selecting the LRU request of the plurality of request groups to access the shared resource.
摘要翻译：一种方法，其包括提供LRU选择逻辑，所述LRU选择逻辑可控制地将经由第一级别和第二级别访问计算机系统资源的请求传递给共享资源，确定请求组中的请求是否是活动的，向LRU选择逻辑呈现请求所述第一级当确定所述请求是活动时，确定所述请求是否是所述第一级请求组的LRU请求，当确定所述请求是所述请求的LRU请求时将所述请求转发到所述第二级别所述请求组将所述请求与来自所述第二级别的每个请求组的LRU请求进行比较，以确定所述请求是否是所述多个请求组的LRU请求，以及选择所述多个请求组的所述LRU请求以访问共享资源。

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