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1. 发明授权

US08036243B2 Single chip protocol converter 失效
标题翻译：单芯片协议转换器
公开(公告)号：US08036243B2
公开(公告)日：2011-10-11
申请号：US12189675
申请日：2008-08-11
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04J3/16
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单个集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。分组转换还可能需要转换根据第一协议版本级别生成的分组，并且处理所述分组以实现根据第二协议版本级别而是在相同协议族类型内生成转换的分组的协议转换。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

2. 发明授权

US07412588B2 Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus 有权
标题翻译：网络处理器系统芯片采用桥耦合协议，将多处理器宏核心局部总线转换为外设接口耦合系统总线
公开(公告)号：US07412588B2
公开(公告)日：2008-08-12
申请号：US10768828
申请日：2004-01-30
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： G06F15/16
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A network processor includes a system-onchip (SoC) macro core and functions as a single chip protocol converter that receives packets generating according to a first protocol type and processes the packets to implement protocol conversion and generates converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the SoC macro core. The process of protocol conversion contained within the SoC macro core does not require the processing resources of a host system. The system-on chip macro core includes a bridge device for coupling a local bus in the protocol converting multiprocessor SoC macro core local bus to peripheral interfaces coupled to a system bus.
摘要翻译：网络处理器包括系统级芯片（SoC）宏核心，并且用作单芯片协议转换器，其接收根据第一协议类型生成的分组，并且处理分组以实现协议转换，并且生成用于输出的第二协议类型的转换分组其协议转换过程完全在SoC宏核心内进行。包含在SoC宏核心内的协议转换过程不需要主机系统的处理资源。系统级芯片宏核心包括用于将协议转换多处理器SoC宏核心局部总线中的局部总线耦合到耦合到系统总线的外设接口的桥接器件。

3. 发明授权

US08811422B2 Single chip protocol converter 有权
标题翻译：单芯片协议转换器
公开(公告)号：US08811422B2
公开(公告)日：2014-08-19
申请号：US13269065
申请日：2011-10-07
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04J3/16 , G06F15/167 , H04L12/56 , G06F15/78
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单一集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

4. 发明申请

US20120082171A1 SINGLE CHIP PROTOCOL CONVERTER 有权
标题翻译：单芯片协议转换器
公开(公告)号：US20120082171A1
公开(公告)日：2012-04-05
申请号：US13269065
申请日：2011-10-07
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04L12/00
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单一集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

5. 发明申请

US20090059955A1 SINGLE CHIP PROTOCOL CONVERTER 失效
标题翻译：单芯片协议转换器
公开(公告)号：US20090059955A1
公开(公告)日：2009-03-05
申请号：US12189675
申请日：2008-08-11
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04J3/22
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单个集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。分组转换还可能需要转换根据第一协议版本级别生成的分组，并且处理所述分组以实现根据第二协议版本级别而是在相同协议族类型内生成转换的分组的协议转换。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

6. 发明授权

US07353362B2 Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus 有权
标题翻译： SoC中的多处理器子系统与处理器集群之间的桥接互连和SoC系统总线
公开(公告)号：US07353362B2
公开(公告)日：2008-04-01
申请号：US10604491
申请日：2003-07-25
申请人： Christos J. Georgiou , Victor L. Gregurick , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Valentina Salapura
IPC分类号： G06F13/36
CPC分类号： G06F15/7832 , H04L49/109 , H04L49/602
摘要： A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.
摘要翻译：一种片上系统（SoC）组件，其包括包括多个多个处理器的单个独立多处理器子系统核心，每个多处理器具有与其相关联的本地存储器形成处理器集群; 并且交换结构意味着连接SoC集成电路（IC）中的每个处理器集群。当配置为DSP，协处理器，混合ASIC或网络处理安排时，单个SoC独立多处理器子系统内核能够对SoC设备执行多线程操作处理。交换结构意味着另外将SoC本地系统总线设备与SoC处理器组件与独立的多处理器子系统核心互连。

7. 发明授权

US07917729B2 System on chip IC with subsystem of multiple processing cores switch coupled to network protocol device and bus bridge to local system bus 有权
标题翻译：具有多处理核心子系统的片上集成电路交换机与网络协议设备和总线桥耦合到本地系统总线
公开(公告)号：US07917729B2
公开(公告)日：2011-03-29
申请号：US11757166
申请日：2007-06-01
申请人： Christos J. Georgiou , Victor L. Gregurick , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Valentina Salapura
IPC分类号： G06F15/16
CPC分类号： G06F15/7832 , H04L49/109 , H04L49/602
摘要： A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.
摘要翻译：一种片上系统（SoC）组件，其包括包括多个多个处理器的单个独立多处理器子系统核心，每个多处理器具有与其相关联的本地存储器形成处理器集群; 并且交换结构意味着连接SoC集成电路（IC）中的每个处理器集群。当配置为DSP，协处理器，混合ASIC或网络处理安排时，单个SoC独立多处理器子系统内核能够对SoC设备执行多线程操作处理。交换结构意味着另外将SoC本地系统总线设备与SoC处理器组件与独立的多处理器子系统核心互连。

8. 发明申请

US20080192749A1 METHOD AND SYSTEM OF EFFICIENT PACKET REORDERING 失效
标题翻译：高效包装的方法与系统
公开(公告)号：US20080192749A1
公开(公告)日：2008-08-14
申请号：US12105968
申请日：2008-04-18
申请人： Christos J. GEORGIOU , Valentina Salapura
发明人： Christos J. GEORGIOU , Valentina Salapura
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/34
摘要： A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list, for a particular flow. A transmission queue and reorder table is used to record the beginning sequence number for each segment. The transmission queue is consulted to locate the segment beginning with the lowest packet sequence number for a flow. The packets associated with the segment are transmitted in order. The transmission queue is then repeatedly searched for the next lowest packet sequence number for transmission of the associated packet chain until the transmission queue is emptied.
摘要翻译：提供了一种方法和系统来有效地排序通过网络接收的分组。该方法通过检测失序分组来检测一个或多个分组流的序列中断，并且将顺序分组的分段进入用于特定流的单独的存储区域，例如链表。传输队列和重排序表用于记录每个段的起始序列号。参考传输队列以定位从流的最低分组序列号开始的分段。与段相关联的分组按顺序传输。然后，重复地搜索传输队列用于相关联的分组链的传输的下一个最低分组序列号，直到传输队列被清空。

9. 发明授权

US07957288B2 Method and system of efficient packet reordering 失效
标题翻译：高效数据包重排序方法及系统
公开(公告)号：US07957288B2
公开(公告)日：2011-06-07
申请号：US12105968
申请日：2008-04-18
申请人： Christos J. Georgiou , Valentina Salapura
发明人： Christos J. Georgiou , Valentina Salapura
IPC分类号： H04J3/14 , H04L12/26
CPC分类号： H04L47/10 , H04L47/34
摘要： A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list, for a particular flow. A transmission queue and reorder table is used to record the beginning sequence number for each segment. The transmission queue is consulted to locate the segment beginning with the lowest packet sequence number for a flow. The packets associated with the segment are transmitted in order. The transmission queue is then repeatedly searched for the next lowest packet sequence number for transmission of the associated packet chain until the transmission queue is emptied.
摘要翻译：提供了一种方法和系统来有效地排序通过网络接收的分组。该方法通过检测失序分组来检测一个或多个分组流的序列中断，并且将顺序分组的分段进入用于特定流的单独的存储区域，例如链表。传输队列和重排序表用于记录每个段的起始序列号。参考传输队列以定位从流的最低分组序列号开始的分段。与段相关联的分组按顺序传输。然后，重复地搜索传输队列用于相关联的分组链的传输的下一个最低分组序列号，直到传输队列被清空。

10. 发明授权

US06904040B2 Packet preprocessing interface for multiprocessor network handler 失效
标题翻译：用于多处理器网络处理程序的数据包预处理接口
公开(公告)号：US06904040B2
公开(公告)日：2005-06-07
申请号：US09682689
申请日：2001-10-05
申请人： Valentina Salapura , Christos J. Georgiou
发明人： Valentina Salapura , Christos J. Georgiou
IPC分类号： H04L12/56
CPC分类号： H04L47/2441 , H04L47/10 , H04L47/125 , H04L49/90
摘要： A network handler uses a DMA device to assign packets to network processors in accordance with a mapping function which classifies packets based on its content, e.g., bits in one or more header fields. Preferably, the mapping function is implemented as a hash function, which uses a predetermined number of bits from packet as inputs. The result of this function specifies the processor to which the packet is assigned. To make implementation manageable in a high-traffic environment, each processor may be equipped with a queue, which holds pointer information. Such a pointer provides an indication of the area in memory where incoming packet resides. The network handler is particularly useful in a Fiber Channel environment, where the hash function may be implemented to assign all packets from the same sequence to the same processor, thereby resulting in improved processing efficiency.
摘要翻译：网络处理器使用DMA设备来根据映射函数向网络处理器分配分组，所述映射函数根据其内容对分组进行分类，例如在一个或多个报头字段中的位。优选地，映射函数被实现为散列函数，其使用来自分组的预定数量的比特作为输入。此功能的结果指定分配给哪个分组的处理器。为了在高流量环境中实现可管理，每个处理器可以配备有保存指针信息的队列。这样的指针提供了输入分组所驻留的存储器中的区域的指示。网络处理器在光纤通道环境中特别有用，其中可以实现散列函数以将相同序列的所有分组分配给同一处理器，从而提高处理效率。

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