专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130316535A1 METHODS OF FORMING SEMICONDUCTOR DEVICES WITH METAL SILICIDE USING PRE-AMORPHIZATION IMPLANTS AND DEVICES SO FORMED 有权
标题翻译：使用预成型植入物和形成的器件形成具有金属硅化物的半导体器件的方法
公开(公告)号：US20130316535A1
公开(公告)日：2013-11-28
申请号：US13788599
申请日：2013-03-07
申请人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-Ik Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
发明人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-Ik Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
IPC分类号： H01L21/28
CPC分类号： H01L29/7839 , H01L21/26506 , H01L21/28 , H01L21/28518 , H01L21/28537 , H01L21/76814 , H01L23/485 , H01L27/092 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/401 , H01L29/665 , H01L29/66636 , H01L29/66643 , H01L29/78 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.
摘要翻译：可以通过形成露出升高的源极/漏极区域的表面的开口来提供形成半导体器件的方法。可以减小开口的尺寸，并且可以通过开口将升高的源极/漏极区域（PAI）进行预非晶化植入（PAI），以形成升高的源极/漏极区域的非晶化部分。金属硅化物可以由金属和非晶化部分形成。

2. 发明授权

US10043902B2 Semiconductor devices with shaped portions of elevated source/drain regions 有权
公开(公告)号：US10043902B2
公开(公告)日：2018-08-07
申请号：US14963731
申请日：2015-12-09
申请人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-Ik Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
发明人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-Ik Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
IPC分类号： H01L29/78 , H01L21/28 , H01L29/66 , H01L29/40 , H01L21/285 , H01L21/265 , H01L29/165 , H01L23/485 , H01L21/768 , H01L27/092 , H01L29/08 , H01L29/16 , H01L29/161
CPC分类号： H01L29/7839 , H01L21/26506 , H01L21/28 , H01L21/28518 , H01L21/28537 , H01L21/76814 , H01L23/485 , H01L27/092 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/401 , H01L29/665 , H01L29/66636 , H01L29/66643 , H01L29/78 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

3. 发明申请

US20160233334A1 SEMICONDUCTOR DEVICES WITH SHAPED PORTIONS OF ELEVATED SOURCE/DRAIN REGIONS 审中-公开
标题翻译：具有高压源/排水区形状的半导体器件
公开(公告)号：US20160233334A1
公开(公告)日：2016-08-11
申请号：US14963731
申请日：2015-12-09
申请人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-Ik Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
发明人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-Ik Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
IPC分类号： H01L29/78 , H01L29/165 , H01L29/161 , H01L29/16 , H01L27/092 , H01L29/08
CPC分类号： H01L29/7839 , H01L21/26506 , H01L21/28 , H01L21/28518 , H01L21/28537 , H01L21/76814 , H01L23/485 , H01L27/092 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/401 , H01L29/665 , H01L29/66636 , H01L29/66643 , H01L29/78 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.
摘要翻译：可以通过形成露出升高的源极/漏极区域的表面的开口来提供形成半导体器件的方法。可以减小开口的尺寸，并且可以通过开口将升高的源极/漏极区域（PAI）进行预非晶化植入（PAI），以形成升高的源极/漏极区域的非晶化部分。金属硅化物可以由金属和非晶化部分形成。

4. 发明授权

US09240323B2 Methods of forming semiconductor devices with metal silicide using pre-amorphization implants 有权
标题翻译：使用前非晶化植入物形成具有金属硅化物的半导体器件的方法
公开(公告)号：US09240323B2
公开(公告)日：2016-01-19
申请号：US13788599
申请日：2013-03-07
申请人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-Ik Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
发明人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-Ik Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
IPC分类号： H01L21/28 , H01L21/265 , H01L29/66 , H01L29/78 , H01L29/165 , H01L21/285 , H01L23/485 , H01L21/768
CPC分类号： H01L29/7839 , H01L21/26506 , H01L21/28 , H01L21/28518 , H01L21/28537 , H01L21/76814 , H01L23/485 , H01L27/092 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/401 , H01L29/665 , H01L29/66636 , H01L29/66643 , H01L29/78 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.
摘要翻译：可以通过形成露出升高的源极/漏极区域的表面的开口来提供形成半导体器件的方法。可以减小开口的尺寸，并且可以通过开口将升高的源极/漏极区域（PAI）进行预非晶化植入（PAI），以形成升高的源极/漏极区域的非晶化部分。金属硅化物可以由金属和非晶化部分形成。

5. 发明申请

US20180331218A1 SEMICONDUCTOR DEVICES WITH SHAPED PORTIONS OF ELEVATED SOURCE/DRAIN REGIONS 审中-公开
公开(公告)号：US20180331218A1
公开(公告)日：2018-11-15
申请号：US16026614
申请日：2018-07-03
申请人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-lk Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
发明人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-lk Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
IPC分类号： H01L29/78 , H01L21/265 , H01L29/66 , H01L29/40 , H01L29/165 , H01L29/161 , H01L29/16 , H01L29/08 , H01L27/092 , H01L23/485 , H01L21/768 , H01L21/285 , H01L21/28
CPC分类号： H01L29/7839 , H01L21/26506 , H01L21/28 , H01L21/28518 , H01L21/28537 , H01L21/76814 , H01L23/485 , H01L27/092 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/401 , H01L29/665 , H01L29/66636 , H01L29/66643 , H01L29/78 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

6. 发明授权

US07692196B2 Memory devices and methods of manufacturing the same 失效
标题翻译：存储器件及其制造方法
公开(公告)号：US07692196B2
公开(公告)日：2010-04-06
申请号：US11655689
申请日：2007-01-19
申请人： In-Sang Jeon , Sang-Bom Kang , Dong-Chan Kim , Chul-Sung Kim , Sug-Hun Hong , Sang-Jin Hyun
发明人： In-Sang Jeon , Sang-Bom Kang , Dong-Chan Kim , Chul-Sung Kim , Sug-Hun Hong , Sang-Jin Hyun
IPC分类号： H01L27/108
CPC分类号： H01L21/28282 , H01L29/513 , H01L29/792 , Y10S257/908
摘要： The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second tunnel insulation layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode on the blocking layer pattern. The memory device further includes a source/drain region at an upper portion of the semiconductor substrate. The upper portion of the semiconductor substrate is adjacent to the first tunnel insulation layer pattern.
摘要翻译：存储器件包括在半导体衬底上的第一隧道绝缘层图案，第二隧道绝缘层图案，其第一隧道绝缘层图案上具有比第一隧道绝缘层图案低的能带隙，第二隧道绝缘层图案，电荷俘获层图案上的阻挡层图案，以及阻挡层图案上的栅电极。存储器件还包括在半导体衬底的上部的源极/漏极区域。半导体衬底的上部与第一隧道绝缘层图案相邻。

7. 发明申请

US20080164508A1 Memory devices and methods of manufacturing the same 失效
标题翻译：存储器件及其制造方法
公开(公告)号：US20080164508A1
公开(公告)日：2008-07-10
申请号：US11655689
申请日：2007-01-19
申请人： In-Sang Jeon , Sang-Bom Kang , Dong-Chan Kim , Chul-Sung Kim , Sug-Hun Hong , Sang-Jin Hyun
发明人： In-Sang Jeon , Sang-Bom Kang , Dong-Chan Kim , Chul-Sung Kim , Sug-Hun Hong , Sang-Jin Hyun
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L29/513 , H01L29/792 , Y10S257/908
摘要： The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second tunnel insulation layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode on the blocking layer pattern. The memory device further includes a source/drain region at an upper portion of the semiconductor substrate, The upper portion of the semiconductor substrate is adjacent to the first tunnel insulation layer pattern.
摘要翻译：存储器件包括在半导体衬底上的第一隧道绝缘层图案，第二隧道绝缘层图案，其第一隧道绝缘层图案上具有比第一隧道绝缘层图案低的能带隙，第二隧道绝缘层图案，电荷俘获层图案上的阻挡层图案，以及阻挡层图案上的栅电极。存储器件还包括在半导体衬底的上部的源极/漏极区域。半导体衬底的上部与第一隧道绝缘层图案相邻。

8. 发明授权

US09768255B2 Semiconductor devices including contact structures that partially overlap silicide layers 有权
公开(公告)号：US09768255B2
公开(公告)日：2017-09-19
申请号：US15006717
申请日：2016-01-26
申请人： Do-Sun Lee , Chang-Woo Sohn , Chul-Sung Kim , Shigenobu Maeda , Young-Moon Choi , Hyo-Seok Choi , Sang-Jin Hyun
发明人： Do-Sun Lee , Chang-Woo Sohn , Chul-Sung Kim , Shigenobu Maeda , Young-Moon Choi , Hyo-Seok Choi , Sang-Jin Hyun
IPC分类号： H01L29/08 , H01L29/06 , H01L29/161 , H01L29/165 , H01L29/78 , H01L29/417
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/7848 , H01L29/785
摘要： Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

9. 发明申请

US20120171826A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120171826A1
公开(公告)日：2012-07-05
申请号：US13243147
申请日：2011-09-23
申请人： Jin-Bum Kim , Chul-Sung Kim , Yu-Gyun Shin , Dae-Yong Kim , Joon-Gon Lee , Kwang-Young Lee
发明人： Jin-Bum Kim , Chul-Sung Kim , Yu-Gyun Shin , Dae-Yong Kim , Joon-Gon Lee , Kwang-Young Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814
摘要： A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.
摘要翻译：制造半导体的方法包括提供具有限定在其中的第一区域和第二区域的衬底，在第一区域中形成第一栅极和第一源极和漏极区域，并在第一区域中形成第二栅极和第二源极和漏极区域在所述第二源极和漏极区域中形成外延层，在所述第一源极和漏极区域中形成第一金属硅化物层，在所述第一区域和所述第二区域上形成层间电介质层，形成多个接触孔，第一金属硅化物层和外延层，同时穿透层间电介质层，在暴露的外延层中形成第二金属硅化物层，并且通过填充多个接触孔形成与第一和第二金属硅化物层接触的多个触点。

10. 发明授权

US08530303B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08530303B2
公开(公告)日：2013-09-10
申请号：US13243147
申请日：2011-09-23
申请人： Jin-Bum Kim , Chul-Sung Kim , Yu-Gyun Shin , Dae-Yong Kim , Joon-Gon Lee , Kwang-Young Lee
发明人： Jin-Bum Kim , Chul-Sung Kim , Yu-Gyun Shin , Dae-Yong Kim , Joon-Gon Lee , Kwang-Young Lee
IPC分类号： H01L21/8249
CPC分类号： H01L21/823807 , H01L21/823814
摘要： A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.
摘要翻译：制造半导体的方法包括提供具有限定在其中的第一区域和第二区域的衬底，在第一区域中形成第一栅极和第一源极和漏极区域，并在第一区域中形成第二栅极和第二源极和漏极区域在所述第二源极和漏极区域中形成外延层，在所述第一源极和漏极区域中形成第一金属硅化物层，在所述第一区域和所述第二区域上形成层间电介质层，形成多个接触孔，第一金属硅化物层和外延层，同时穿透层间电介质层，在暴露的外延层中形成第二金属硅化物层，并且通过填充多个接触孔形成与第一和第二金属硅化物层接触的多个触点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式