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    • 3. 发明授权
    • Backlight module
    • 背光模组
    • US08827535B2
    • 2014-09-09
    • US12833054
    • 2010-07-09
    • Ci-Guang PengTe-Hen LoCheng-Yu WangMing-Sheng Lai
    • Ci-Guang PengTe-Hen LoCheng-Yu WangMing-Sheng Lai
    • F21V8/00F21V21/00
    • G02B6/0031G02B6/0055G02B6/0088
    • This present invention discloses a backlight module including a frame and a light guide plate. The frame includes a base plane and a side wall, wherein the side wall is disposed at the edge of the base plane and encloses a disposition space. The side wall includes a first inner surface and an outer surface, wherein a distance between the first inner surface and the outer surface is decreased as the first inner surface comes closer to a bottom of the side wall. The light guide plate is disposed on the base plane and within the disposition space, wherein the first inner surface sinks toward the outer surface and a recessed space is formed between the first inner surface and a lateral side of the light guide plate.
    • 本发明公开了一种背光模块,其包括框架和导光板。 框架包括基面和侧壁,其中侧壁设置在基面的边缘并且包围配置空间。 侧壁包括第一内表面和外表面,其中当第一内表面靠近侧壁的底部时,第一内表面和外表面之间的距离减小。 导光板设置在基面上并位于配置空间内,其中第一内表面向外表面凹陷,并且在导光板的第一内表面和横向侧之间形成凹陷空间。
    • 5. 发明授权
    • Liquid crystal display and driving method thereof
    • 液晶显示及其驱动方法
    • US08766889B2
    • 2014-07-01
    • US12056355
    • 2008-03-27
    • Ming-Sheng LaiChih-Wei WangHsueh-Ying HuangChen-Kuo Yang
    • Ming-Sheng LaiChih-Wei WangHsueh-Ying HuangChen-Kuo Yang
    • G09G3/36
    • G09G3/3659G09G3/3614G09G2300/0443G09G2300/0447G09G2300/0809G09G2300/0876G09G2310/0281G09G2320/028
    • A liquid crystal display and a driving method thereof are provided. The liquid crystal display includes a plurality of pixels, a plurality of scan lines, and a plurality of data lines. Each pixel includes a plurality of sub-pixels. Each sub-pixel is coupled to the data line, and includes a switch, a storage capacitor, and a sub-pixel electrode. The switch is coupled to a scan line to receive a scan signal. The switch is turned on by the scan signal to receive a data signal transmitted from the data line. The storage capacitors of the sub-pixels of each pixel are coupled to the scan lines, or the storage capacitor of one of the sub-pixels of each pixel is coupled to a common electrode and the storage capacitors of the other sub-pixels are coupled to the scan lines. The switch and the storage capacitor of each sub-pixel are coupled to different scan lines. The method includes transmitting the scan signal having a plurality of voltage levels to modulate the voltage levels of one or more sub-pixel electrodes of the sub-pixels of the same pixel, thereby enabling the sub-pixels of the same pixel to have different voltage levels.
    • 提供了一种液晶显示器及其驱动方法。 液晶显示器包括多个像素,多条扫描线和多条数据线。 每个像素包括多个子像素。 每个子像素耦合到数据线,并且包括开关,存储电容器和子像素电极。 开关耦合到扫描线以接收扫描信号。 开关由扫描信号接通,以接收从数据线发送的数据信号。 每个像素的子像素的存储电容器耦合到扫描线,或者每个像素的一个子像素的存储电容器耦合到公共电极,并且其他子像素的存储电容器被耦合 到扫描线。 每个子像素的开关和存储电容器耦合到不同的扫描线。 该方法包括发送具有多个电压电平的扫描信号,以调制相同像素的子像素的一个或多个子像素电极的电压电平,从而使相同像素的子像素具有不同的电压 水平。
    • 6. 发明授权
    • Shift register of LCD devices
    • LCD设备的移位寄存器
    • US08340240B2
    • 2012-12-25
    • US13492916
    • 2012-06-10
    • Tsung-Ting TsaiMing-Sheng LaiMin-Feng ChiangChun-Hsin Liu
    • Tsung-Ting TsaiMing-Sheng LaiMin-Feng ChiangChun-Hsin Liu
    • G11C19/00
    • G11C19/00G09G3/3677G09G2300/0408G09G2310/0286G09G2320/0219G11C19/28
    • A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.
    • 移位寄存器包括串联耦合的多个移位寄存器单元。 接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点,上拉驱动电路,上拉电路和第一至第三下拉电路。 上拉驱动电路可以将输入电压传输到节点,并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。 第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。 第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。 第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。
    • 9. 发明授权
    • Shift register
    • 移位寄存器
    • US07817771B2
    • 2010-10-19
    • US12334874
    • 2008-12-15
    • Tsung-Ting TsaiMing-Sheng LaiMin-Feng ChiangPo-Yuan Liu
    • Tsung-Ting TsaiMing-Sheng LaiMin-Feng ChiangPo-Yuan Liu
    • G11C19/00
    • G11C19/28
    • A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
    • 移位寄存器包括多个级,{Sn},n = 1,2。 。 。 ,N,N为正整数。 在一个实施例中,每级Sn包括一个上拉电路,该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端,用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时,上拉控制电路响应地产生提供给输入节点Qn的信号,以接通上拉电路, 电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路,以及被配置为接收一个电压的下拉控制电路 第三时钟信号CK2和第四时钟信号XCK2,并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和 阶段Sn + 1。