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1. 发明授权

US08913359B2 Latch-up free RC-based NMOS ESD power clamp in HV use 有权
标题翻译：高压使用中的无闩锁RC型NMOS ESD功率钳
公开(公告)号：US08913359B2
公开(公告)日：2014-12-16
申请号：US13710700
申请日：2012-12-11
申请人： Da-Wei Lai , Ying-Chang Lin , Handoko Linewih
发明人： Da-Wei Lai , Ying-Chang Lin , Handoko Linewih
IPC分类号： H02H3/22 , H02H9/04
CPC分类号： H02H9/044 , H01L27/0274 , H01L27/0277 , H02H9/046
摘要： An RC-based electrostatic discharge protection device provides an extended snapback trigger voltage range, thereby avoiding latch-up. Two parallel current discharge paths are provided between supply terminals during an electrostatic discharge event by virtue of an added external resistor. The first current discharge path includes body resistance of the protection device and the second current discharge path includes the external resistor.
摘要翻译：基于RC的静电放电保护装置提供扩展的快速恢复触发电压范围，从而避免闩锁。在静电放电事件期间，通过附加的外部电阻器，在电源端子之间提供两个并联电流放电路径。第一电流放电路径包括保护装置的体电阻，第二电流放电路径包括外部电阻器。

2. 发明授权

US08891215B2 High noise immunity with latch-up free ESD clamp 有权
标题翻译：高抗噪声，具有无闩锁的ESD钳位
公开(公告)号：US08891215B2
公开(公告)日：2014-11-18
申请号：US13711141
申请日：2012-12-11
申请人： Da-Wei Lai , Handoko Linewih , Ying-Chang Lin
发明人： Da-Wei Lai , Handoko Linewih , Ying-Chang Lin
IPC分类号： H02H9/00 , H02H9/04 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22
CPC分类号： H02H9/04 , H01L27/0274 , H01L27/0285 , H02H9/043 , H02H9/046 , Y10T29/49117
摘要： A triple stack NMOS integrated circuit structure protection circuit for a plurality of terminals operative at respective voltage levels is coupled between the plurality of terminals. First and second NMOS elements of the triple stack NMOS share a common active region. A third NMOS element, vertically positioned with respect to the first and second NMOS elements, has an active region separate from the active region of the first and second NMOS elements. The first, second and third NMOS elements are connected in series between two terminals of the plurality of terminals.
摘要翻译：用于在各个电压电平下工作的多个终端的三重堆叠的NMOS集成电路结构保护电路耦合在多个终端之间。三重堆叠NMOS的第一和第二NMOS元件共享公共有源区。相对于第一和第二NMOS元件垂直定位的第三NMOS元件具有与第一和第二NMOS元件的有源区分离的有源区。第一，第二和第三NMOS元件串联连接在多个端子的两个端子之间。

3. 发明授权

US08710545B2 Latch-up free ESD protection 有权
标题翻译：免维护ESD保护
公开(公告)号：US08710545B2
公开(公告)日：2014-04-29
申请号：US13533959
申请日：2012-06-26
申请人： Da-Wei Lai , Handoko Linewih
发明人： Da-Wei Lai , Handoko Linewih
IPC分类号： H01L29/74
CPC分类号： H01L27/0262 , H01L29/7436
摘要： An ESD module having a first portion (FP) and a second portion (SP) in a substrate is presented. The FP includes a FP well of a second polarity type and first and second FP contact regions. The first FP contact region is of a first polarity type and the second FP contact region is of a second polarity type. The SP includes a SP well of a first polarity type and first and second SP contact regions. The first SP contact region is of a first polarity type and the second SP contact region is of a second polarity type. An intermediate portion (IP) is disposed in the substrate between the FP and SP in the substrate. The IP includes a well of the second polarity type. The IP increases trigger current and holding voltage of the module to prevent latch up during normal device operation.
摘要翻译：提出了一种在衬底中具有第一部分（FP）和第二部分（SP）的ESD模块。 FP包括第二极性类型的FP阱和第一和第二FP接触区域。第一FP接触区域是第一极性类型，第二FP接触区域是第二极性类型。 SP包括第一极性类型和第一和第二SP接触区域的SP阱。第一SP接触区域是第一极性类型，第二SP接触区域是第二极性类型。在衬底中的FP和SP之间的衬底中设置中间部分（IP）。 IP包括第二极性类型的阱。 IP增加模块的触发电流和保持电压，以防止在正常设备操作期间锁定。

4. 发明申请

US20050152080A1 Integrated electronic disconnecting circuits, methods, and systems 有权
标题翻译：集成电子断路电路，方法和系统
公开(公告)号：US20050152080A1
公开(公告)日：2005-07-14
申请号：US10924763
申请日：2004-08-23
申请人： Richard Harris , Handoko Linewih
发明人： Richard Harris , Handoko Linewih
IPC分类号： H01L27/098 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/808 , H02H9/00
CPC分类号： H01L29/7802 , H01L27/098 , H01L29/0657 , H01L29/0696 , H01L29/0847 , H01L29/1095 , H01L29/7827 , H01L29/8083
摘要： Merged devices for transient blocking. A pass transistor is placed so that its body potential drives the gate of a depletion-mode JFET-type blocking transistor. Thus a transient which appears on an external terminal is very rapidly propagated to shut off the blocking transistor, before large numbers of carriers can be injected. Preferably a shunt device is also used to drop high potentials which may appear at the same time. This connection can be particularly useful in power or data input terminals.
摘要翻译：用于瞬态阻塞的合并设备。放置传输晶体管，使其体电位驱动耗尽型JFET型阻断晶体管的栅极。因此，在可以注入大量载流子之前，出现在外部端子上的瞬变被非常快速地传播以截止阻塞晶体管。优选地，分流装置也用于降低可能同时出现的高电位。这种连接在电源或数据输入端子中特别有用。

5. 发明授权

US07262946B2 Integrated electronic disconnecting circuits, methods, and systems 有权
标题翻译：集成电子断路电路，方法和系统
公开(公告)号：US07262946B2
公开(公告)日：2007-08-28
申请号：US10924763
申请日：2004-08-23
申请人： Richard Harris , Handoko Linewih
发明人： Richard Harris , Handoko Linewih
IPC分类号： H02H3/20
CPC分类号： H01L29/7802 , H01L27/098 , H01L29/0657 , H01L29/0696 , H01L29/0847 , H01L29/1095 , H01L29/7827 , H01L29/8083
摘要： Merged devices for transient blocking. A pass transistor is placed so that its body potential drives the gate of a depletion-mode JFET-type blocking transistor. Thus a transient which appears on an external terminal is very rapidly propagated to shut off the blocking transistor, before large numbers of carriers can be injected. Preferably a shunt device is also used to drop high potentials which may appear at the same time. This connection can be particularly useful in power or data input terminals.
摘要翻译：用于瞬态阻塞的合并设备。放置传输晶体管，使其体电位驱动耗尽型JFET型阻断晶体管的栅极。因此，在可以注入大量载流子之前，出现在外部端子上的瞬变被非常快速地传播以截止阻塞晶体管。优选地，分流装置也用于降低可能同时出现的高电位。这种连接在电源或数据输入端子中特别有用。

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