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1. 发明申请

US20130235496A1 ESD-ROBUST I/O DRIVER CIRCUITS 有权
标题翻译： ESD-ROBUST I / O驱动电路
公开(公告)号：US20130235496A1
公开(公告)日：2013-09-12
申请号：US13415178
申请日：2012-03-08
申请人： Da-Wei Lai , Ying-Chang Lin , Mahadeva Iyer Natarajan
发明人： Da-Wei Lai , Ying-Chang Lin , Mahadeva Iyer Natarajan
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source to a ground rail and the first drain to an I/O pad; coupling a gate driver control circuit to the first drain and the first gate; and providing a ground potential to the first gate, via the gate driver control circuit, during an ESD event occurring from the I/O pad to the ground rail.
摘要翻译：公开了一种ESD稳健的I / O驱动器电路。实施例包括提供具有第一源极，第一漏极和第一栅极的第一NMOS晶体管; 将第一源耦合到接地导轨，将第一漏极耦合到I / O焊盘; 将栅极驱动器控制电路耦合到所述第一漏极和所述第一栅极; 以及在从I / O焊盘发生到地轨的ESD事件期间，经由栅极驱动器控制电路向第一栅极提供接地电位。

2. 发明授权

US08724271B2 ESD-robust I/O driver circuits 有权
标题翻译： ESD稳健的I / O驱动电路
公开(公告)号：US08724271B2
公开(公告)日：2014-05-13
申请号：US13415178
申请日：2012-03-08
申请人： Da-Wei Lai , Ying-Chang Lin , Mahadeva Iyer Natarajan
发明人： Da-Wei Lai , Ying-Chang Lin , Mahadeva Iyer Natarajan
IPC分类号： H02H3/22
CPC分类号： H02H9/046
摘要： An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source to a ground rail and the first drain to an I/O pad; coupling a gate driver control circuit to the first drain and the first gate; and providing a ground potential to the first gate, via the gate driver control circuit, during an ESD event occurring from the I/O pad to the ground rail.
摘要翻译：公开了一种ESD稳健的I / O驱动器电路。实施例包括提供具有第一源极，第一漏极和第一栅极的第一NMOS晶体管; 将第一源耦合到接地导轨，将第一漏极耦合到I / O焊盘; 将栅极驱动器控制电路耦合到所述第一漏极和所述第一栅极; 以及在从I / O焊盘发生到地轨的ESD事件期间，经由栅极驱动器控制电路向第一栅极提供接地电位。

3. 发明授权

US09154122B2 Latch up detection 有权
标题翻译：锁定检测
公开(公告)号：US09154122B2
公开(公告)日：2015-10-06
申请号：US13406534
申请日：2012-02-28
申请人： Da-Wei Lai , Mahadeva Iyer Natarajan
发明人： Da-Wei Lai , Mahadeva Iyer Natarajan
IPC分类号： H03K17/082 , H01L23/62 , H01L27/092
CPC分类号： H03K17/082 , H01L23/62 , H01L27/0921 , H01L2924/0002 , H01L2924/00
摘要： A device is presented. The device includes a first circuit coupled to first and second power rails of the device. The first circuit is subject to a latch up event in the presence of a latch up condition. The latch up event includes a low resistance path created between the first and second power rails. The device also includes a latch up sensing (LUS) circuit coupled to the first circuit. The LUS circuit is configured to receive a LUS input signal from the first circuit and generates a LUS output signal to the first circuit. When the input signal is an active latch up signal which indicates the presence of a latch up condition, the LUS circuit generates an active LUS output signal which creates a break in the low resistance path to terminate the latch up event.
摘要翻译：提供了一个设备。该装置包括耦合到该装置的第一和第二电力轨的第一电路。在存在闩锁状态的情况下，第一电路经历闩锁事件。闩锁事件包括在第一和第二电源轨之间产生的低电阻路径。该装置还包括耦合到第一电路的闭锁检测（LUS）电路。 LUS电路被配置为从第一电路接收LUS输入信号并且产生到第一电路的LUS输出信号。当输入信号是指示存在锁存状态的有效锁存信号时，LUS电路产生有效的LUS输出信号，该信号在低电阻路径中产生中断以终止锁存事件。

4. 发明授权

US08964341B2 Gate dielectric protection 有权
标题翻译：栅介质保护
公开(公告)号：US08964341B2
公开(公告)日：2015-02-24
申请号：US13457453
申请日：2012-04-26
申请人： Manjunatha Govinda Prabhu , Mahadeva Iyer Natarajan , Da-Wei Lai , Ryan Shan
发明人： Manjunatha Govinda Prabhu , Mahadeva Iyer Natarajan , Da-Wei Lai , Ryan Shan
IPC分类号： H02H9/04 , H02H3/20
CPC分类号： H01L27/0248 , H02H9/046
摘要： Protecting a gate dielectric is achieved with a gate dielectric protection circuit coupled to a transistor at risk. The protection circuit is activated to reduce the voltage across the gate dielectric (VDIFF) to below its breakdown voltage (VBD). The protection circuit is activated when an ESD event is detected. The protection circuit provides a protection or ESD bias to reduce VDIFF below VBD.
摘要翻译：栅极电介质的保护是通过栅极电介质保护电路来实现的，该栅极介质保护电路与处于危险中的晶体管耦合。激活保护电路以将栅极电介质（VDIFF）上的电压降低到其击穿电压（VBD）以下。当检测到ESD事件时，保护电路被激活。保护电路提供保护或ESD偏置，以将VDIFF降低到低于VBD。

5. 发明授权

US08913357B2 ESD protection circuit 有权
标题翻译： ESD保护电路
公开(公告)号：US08913357B2
公开(公告)日：2014-12-16
申请号：US13485932
申请日：2012-06-01
申请人： Da-Wei Lai , Mahadeva Iyer Natarajan
发明人： Da-Wei Lai , Mahadeva Iyer Natarajan
IPC分类号： H02H9/04
CPC分类号： H01L27/0248 , H01L27/0259 , H02H9/04 , H02H9/041 , H02H9/042 , Y10T29/49224
摘要： An ESD circuit is disclosed. The ESD circuit includes a pad and a ground and a sensing element coupled between the pad and ground for sensing an ESD current. The sensing element generates an active sense output signal when an ESD current is sensed and an inactive sense output signal when no ESD current is sensed. The ESD circuit also includes a bypass element comprising a bi-polar junction transistor. The bypass element is coupled in parallel to the sensing element between the pad and ground. The active sense output signal causes the bypass element to be activated to provide a current path between the pad and ground.
摘要翻译：公开了ESD电路。 ESD电路包括焊盘和接地以及耦合在焊盘和接地之间以感测ESD电流的感测元件。当感测到ESD电流时，感测元件产生有源感测输出信号，而当感测不到ESD电流时，感测元件产生无源感测输出信号。 ESD电路还包括包括双极结型晶体管的旁路元件。旁路元件与焊盘和接地之间的感测元件并联耦合。主动感测输出信号使旁路元件被激活，以提供垫和地之间的电流路径。

6. 发明授权

US08778743B2 Latch-up robust PNP-triggered SCR-based devices 有权
标题翻译：锁存稳健的基于PNP触发的基于SCR的器件
公开(公告)号：US08778743B2
公开(公告)日：2014-07-15
申请号：US13588014
申请日：2012-08-17
申请人： Da-Wei Lai , Mahadeva Iyer Natarajan
发明人： Da-Wei Lai , Mahadeva Iyer Natarajan
IPC分类号： H01L21/332 , H01L23/62
CPC分类号： H01L29/7436
摘要： An approach for providing a latch-up robust PNP-triggered SCR-based device is disclosed. Embodiments include providing a silicon control rectifier (SCR) region; providing a PNP region having a first n-well region proximate the SCR region, a first N+ region and a first P+ region in the first n-well region, and a second P+ region between the SCR region and the first n-well region; coupling the first N+ region and the first P+ region to a power rail; and coupling the second P+ region to a ground rail.
摘要翻译：本发明公开了一种用于提供可靠的PNP触发的基于SCR的器件的方法。实施例包括提供硅控整流器（SCR）区域; 提供具有靠近SCR区域的第一n阱区域的PNP区域，第一n阱区域中的第一N +区域和第一P +区域以及SCR区域和第一n阱区域之间的第二P +区域; 将第一N +区域和第一P +区域耦合到电力轨道; 以及将所述第二P +区域耦合到地轨。

7. 发明授权

US08913358B2 Latch-up immune ESD protection 有权
标题翻译：锁定免疫ESD保护
公开(公告)号：US08913358B2
公开(公告)日：2014-12-16
申请号：US13535314
申请日：2012-06-27
申请人： Da-Wei Lai , Mahadeva Iyer Natarajan
发明人： Da-Wei Lai , Mahadeva Iyer Natarajan
IPC分类号： H02H9/00
CPC分类号： H01L27/0262
摘要： An ESD module is presented. The ESD module includes an ESD circuit and a latch-up (LU) control circuit. The ESD circuit has a pad terminal and a low power source terminal. The LU control circuit includes a first LU terminal coupled to a high power source and an LU output terminal coupled to the ESD circuit. The ESD module has first and second operating modes. In the first operating mode, the LU control circuit is deactivated and the ESD circuit has a first triggering current It1 which is less than 100 mA. In the second operating mode, the LU control circuit is activated and the ESD circuit has a second triggering current It2 which is greater than 100 mA.
摘要翻译：介绍了ESD模块。 ESD模块包括ESD电路和闭锁（LU）控制电路。 ESD电路具有焊盘端子和低电源端子。 LU控制电路包括耦合到高电源的第一LU端子和耦合到ESD电路的LU输出端子。 ESD模块具有第一和第二操作模式。在第一种工作模式下，LU控制电路被停用，ESD电路具有小于100mA的第一触发电流It1。在第二种工作模式下，LU控制电路被激活，ESD电路具有大于100mA的第二触发电流It2。

8. 发明授权

US08879221B2 ESD protection without latch-up 有权
标题翻译： ESD保护无闩锁
公开(公告)号：US08879221B2
公开(公告)日：2014-11-04
申请号：US13406537
申请日：2012-02-28
申请人： Da-Wei Lai , Mahadeva Iyer Natarajan , Manjunatha Govinda Prabhu , Ryan Shan
发明人： Da-Wei Lai , Mahadeva Iyer Natarajan , Manjunatha Govinda Prabhu , Ryan Shan
IPC分类号： H02H9/04 , H02H3/20
CPC分类号： H02H9/046 , Y10T29/49117
摘要： A device having an ESD module is disclosed. The ESD module includes an ESD circuit coupled between first and second rails and a control circuit coupled between the rails and to the ESD circuit. When the control circuit senses an ESD event, it causes the ESD circuit to create a current path between the rails to dissipate ESD current. When no ESD event is sensed, the control circuit ensures that no current path is created between the rails to prevent latch-up.
摘要翻译：公开了具有ESD模块的装置。 ESD模块包括耦合在第一和第二导轨之间的ESD电路和耦合在轨道和ESD电路之间的控制电路。当控制电路感测到ESD事件时，会使ESD电路在轨道之间产生电流路径，以消耗ESD电流。当没有感测到ESD事件时，控制电路确保在轨道之间不产生电流路径以防止闩锁。

9. 发明申请

US20140049313A1 LATCH-UP ROBUST PNP-TRIGGERED SCR-BASED DEVICES 有权
标题翻译： LATCH-UP基于PNP触发的基于SCR的器件
公开(公告)号：US20140049313A1
公开(公告)日：2014-02-20
申请号：US13588014
申请日：2012-08-17
申请人： Da-Wei LAI , Mahadeva Iyer Natarajan
发明人： Da-Wei LAI , Mahadeva Iyer Natarajan
IPC分类号： H01L29/73 , G05F3/02
CPC分类号： H01L29/7436
摘要： An approach for providing a latch-up robust PNP-triggered SCR-based device is disclosed. Embodiments include providing a silicon control rectifier (SCR) region; providing a PNP region having a first n-well region proximate the SCR region, a first N+ region and a first P+ region in the first n-well region, and a second P+ region between the SCR region and the first n-well region; coupling the first N+ region and the first P+ region to a power rail; and coupling the second P+ region to a ground rail.
摘要翻译：本发明公开了一种用于提供可靠的PNP触发的基于SCR的器件的方法。实施例包括提供硅控整流器（SCR）区域; 提供具有靠近SCR区域的第一n阱区域的PNP区域，第一n阱区域中的第一N +区域和第一P +区域以及SCR区域和第一n阱区域之间的第二P +区域; 将第一N +区域和第一P +区域耦合到电力轨道; 以及将所述第二P +区域耦合到地轨。

10. 发明授权

US08908341B2 Power clamp for high voltage integrated circuits 有权
标题翻译：高压集成电路的电源钳
公开(公告)号：US08908341B2
公开(公告)日：2014-12-09
申请号：US13439426
申请日：2012-04-04
申请人： Manjunatha Prabhu , Mahadeva Iyer Natarajan , Da-Wei Lai , Shan Ryan
发明人： Manjunatha Prabhu , Mahadeva Iyer Natarajan , Da-Wei Lai , Shan Ryan
IPC分类号： H02H9/00 , H02H9/04 , H02H3/20 , H02H3/22
CPC分类号： H02H9/046
摘要： A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.
摘要翻译：钳位电路包括串联连接在诸如集成电路板的电压源端子和地之间的nmos和pmos器件。连接在电压源和地之间的触发单元包括耦合到钳位电路的多个输出端子。触发单元响应于电压源和地之间的电压阈值，例如由ESD发生引起的电压阈值，以在其输出端施加钳位信号，以通过nmos和pmos器件将电压源端子耦合到地。

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