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1. 发明申请

US20100259982A1 FLASH MEMORY DEVICE AND METHOD OF CONTROLLING FLASH MEMORY DEVICE 有权
标题翻译：闪速存储器件及其控制闪速存储器件的方法
公开(公告)号：US20100259982A1
公开(公告)日：2010-10-14
申请号：US12822246
申请日：2010-06-24
申请人： Dae-Seok Byeon , Young-Ho Lim
发明人： Dae-Seok Byeon , Young-Ho Lim
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/10 , G11C8/10 , G11C8/12 , G11C29/806 , G11C29/844
摘要： A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.
摘要翻译：闪速存储器件包括多个存储器块，被配置为响应于块选择信号来选择至少一个存储器块的解码器，被配置为响应于块地址产生块选择信号并且产生标志信号的控制器，块地址对应于坏块，并且输出缓冲器被配置为响应于指示块地址对应于坏块的标志信号输出固定数据。当块地址对应于坏块时，控制器产生块选择信号以使解码器中断对应于块地址的存储块的选择。

2. 发明授权

US07768831B2 Flash memory device and method of controlling flash memory device 有权
标题翻译：闪存设备及控制闪存设备的方法
公开(公告)号：US07768831B2
公开(公告)日：2010-08-03
申请号：US12109466
申请日：2008-04-25
申请人： Dae-Seok Byeon , Young-Ho Lim
发明人： Dae-Seok Byeon , Young-Ho Lim
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C8/10 , G11C8/12 , G11C29/806 , G11C29/844
摘要： A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, and a controller configured to generate the block select signals in response to a block address. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.
摘要翻译：闪存器件包括多个存储器块，被配置为响应于块选择信号来选择至少一个存储器块的解码器，以及被配置为响应于块地址产生块选择信号的控制器。当块地址对应于坏块时，控制器产生块选择信号以使解码器中断对应于块地址的存储块的选择。

3. 发明授权

US07414890B2 Semiconductor device including a high voltage generation circuit and method of a generating high voltage 有权
标题翻译：包括高电压产生电路和产生高电压的方法的半导体器件
公开(公告)号：US07414890B2
公开(公告)日：2008-08-19
申请号：US11605227
申请日：2006-11-29
申请人： Dae-Seok Byeon , Young-Ho Lim
发明人： Dae-Seok Byeon , Young-Ho Lim
IPC分类号： G11C16/04 , G11C5/14
CPC分类号： G11C16/30 , G11C5/145 , G11C8/10 , G11C16/0483 , G11C16/08 , H02M3/07
摘要： A semiconductor memory device comprises a first pump clock generator configured to generate a first pump clock signal based on a first power supply voltage. The device also comprises a first charge pump configured to generate a first pump output voltage in response to the first pump clock signal. The device also comprises a second pump clock generator configured to generate a second pump clock signal based on the first pump output voltage. The device also comprises a second charge pump configured to generate a second pump output voltage in response to the second pump clock signal. The device also comprises a third pump clock generator configured to generate a third pump clock signal based on the first power supply voltage. The device also comprises a third charge pump configured to generate a third pump output voltage in response to the third pump clock signal.
摘要翻译：半导体存储器件包括被配置为基于第一电源电压产生第一泵时钟信号的第一泵时钟发生器。该装置还包括配置成响应于第一泵时钟信号产生第一泵输出电压的第一电荷泵。该装置还包括被配置为基于第一泵输出电压产生第二泵时钟信号的第二泵时钟发生器。该装置还包括配置成响应于第二泵时钟信号产生第二泵输出电压的第二电荷泵。该装置还包括配置成基于第一电源电压产生第三泵时钟信号的第三泵时钟发生器。该装置还包括配置成响应于第三泵时钟信号产生第三泵输出电压的第三电荷泵。

4. 发明授权

US07397706B2 Methods of erasing flash memory devices by applying wordline bias voltages having multiple levels and related flash memory devices 有权
标题翻译：通过应用具有多个电平的字线偏置电压和相关闪存器件来擦除闪速存储器件的方法
公开(公告)号：US07397706B2
公开(公告)日：2008-07-08
申请号：US11381556
申请日：2006-05-04
申请人： Dae-Seok Byeon , Young-Ho Lim
发明人： Dae-Seok Byeon , Young-Ho Lim
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/16
摘要： Methods of erasing data in a flash memory device are provided in which a plurality of wordline bias voltages are generated that include wordline bias voltages having at least two different levels, erasing data by applying the different wordline bias voltages to respective ones of a plurality of wordlines while applying an erasing voltage to a bulk region of memory cells, and verifying the erased states of the memory cells. Pursuant to these methods, the spread of the threshold-voltage distribution profile that may result from deviations of erasure-coupling ratios between memory cells may be reduced.
摘要翻译：提供擦除闪速存储器件中的数据的方法，其中产生多个字线偏置电压，其包括具有至少两个不同电平的字线偏置电压，通过将不同的字线偏置电压施加到多个字线中的相应字线来擦除数据同时将擦除电压施加到存储器单元的主体区域，以及验证存储器单元的擦除状态。根据这些方法，可能会降低可能由存储器单元之间的擦除耦合比的偏差导致的阈值 - 电压分布曲线的扩展。

5. 发明授权

US06590442B2 Voltage boosting circuit for an integrated circuit device 失效
公开(公告)号：US06590442B2
公开(公告)日：2003-07-08
申请号：US09877811
申请日：2001-10-11
申请人： Dae-Seok Byeon , Young-Ho Lim
发明人： Dae-Seok Byeon , Young-Ho Lim
IPC分类号： G05F324
CPC分类号： G11C5/145 , G11C16/30
摘要： A voltage boosting circuit for an integrated circuit includes a booster and a voltage clamp circuit. The booster generates a boosted voltage higher than the supply voltage in response to a boosting control signal. The voltage clamp circuit includes a voltage detector, a pulse generator, and a discharge circuit. The voltage detector generates, in response to the boosting control signal, a detected voltage signal representing an attribute of the boosted voltage. The pulse generator generates a pulse signal responsive to the detected voltage signal. And the discharge circuit discharges the boosted voltage during an activation period of the pulse signal. This largely stabilizes the output voltage of the booster.

6. 发明授权

US06542406B2 Row decoder of a NOR-type flash memory device 失效
公开(公告)号：US06542406B2
公开(公告)日：2003-04-01
申请号：US09905612
申请日：2001-07-13
申请人： Dae-Seok Byeon , Myung-Jae Kim , Young-Ho Lim , Seung-Keun Lee
发明人： Dae-Seok Byeon , Myung-Jae Kim , Young-Ho Lim , Seung-Keun Lee
IPC分类号： G11C1604
CPC分类号： G11C8/10 , G11C8/12 , G11C16/08
摘要： A nonvolatile semiconductor memory device includes a plurality of first wordlines, a plurality of second wordlines coupled to memory cells, the second wordlines being assigned to each of memory sectors, a plurality of transistors each of which connects a first wordline to a second wordline, and a circuit for controlling the transistors in common. One of the first wordlines is connected to one of the second wordlines through one of the transistors. A circuit area for decoding is reduced and current consumption is minimized.

7. 发明申请

US20110044108A1 FLASH MEMORY DEVICE AND PROGRAM METHOD OF FLASH MEMORY DEVICE USING DIFFERENT VOLTAGES 有权
标题翻译：使用不同电压的闪存存储器件的闪速存储器件和程序方法
公开(公告)号：US20110044108A1
公开(公告)日：2011-02-24
申请号：US12939251
申请日：2010-11-04
申请人： Dae-Seok Byeon , Young-Ho Lim
发明人： Dae-Seok Byeon , Young-Ho Lim
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/10
摘要： A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.
摘要翻译：闪速存储器和闪速存储器的编程方法包括对字线施加通过电压以升高被释放到接地电压的通道电压。一个编程电压被施加到所选择的字线，并且当编程电压被施加到所选择的字线时，局部电压被施加到提供有通过电压的至少一个字线。局部电压低于通过电压，等于或高于接地电压。在将编程电压施加到所选择的字线之前，升压的通道电压可以被放电。

8. 发明申请

US20070074194A1 Methods for programming flash memory devices using variable initial program loops and related devices 有权
标题翻译：使用可变初始程序循环和相关设备编程闪存设备的方法
公开(公告)号：US20070074194A1
公开(公告)日：2007-03-29
申请号：US11439797
申请日：2006-05-24
申请人： Wook-Ghee Hahn , Young-Ho Lim , Dae-Seok Byeon
发明人： Wook-Ghee Hahn , Young-Ho Lim , Dae-Seok Byeon
IPC分类号： G06F9/45
CPC分类号： G11C16/30 , G11C5/145 , G11C8/08 , G11C16/04 , G11C16/08 , G11C16/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： A method of programming a nonvolatile memory device including a plurality of memory cells includes providing a plurality of program loops having a corresponding plurality of program voltages associated therewith. A first one of the plurality of program loops is activated to generate a first program voltage to program a first one of the plurality of memory cells. A second one of the plurality of program loops is activated to generate a second program voltage to program a second one of the plurality of memory cells. Related devices are also discussed.
摘要翻译：包括多个存储器单元的非易失性存储器件的编程方法包括提供具有与其相关联的相应多个编程电压的多个程序循环。多个程序循环中的第一个被激活以产生第一编程电压以编程多个存储器单元中的第一个。多个程序循环中的第二个程序循环被激活以产生第二编程电压以编程多个存储器单元中的第二个。还讨论了相关设备。

9. 发明授权

US06545910B2 Non-volatile semiconductor memory device having word line defect check circuit 有权
标题翻译：具有字线缺陷检查电路的非易失性半导体存储器件
公开(公告)号：US06545910B2
公开(公告)日：2003-04-08
申请号：US09982316
申请日：2001-10-18
申请人： Dae-Seok Byeon , Heung-Soo Im , Young-Ho Lim
发明人： Dae-Seok Byeon , Heung-Soo Im , Young-Ho Lim
IPC分类号： G11C1604
CPC分类号： G11C29/02
摘要： Disclosed is a non-volatile semiconductor memory device provided therein.with a word line defect check circuit. The non-volatile semiconductor memory device includes: a memory cell array including a plurality of cell array blocks including a plurality of cell strings that consist of floating gate memory cell transistors that its drain-source channels are in series connected each other between string select transistors and ground select transistors and that its control gates are correspondingly connected to a plurality of word lines, and a word line short check circuit that inputs different levels of voltage to each of the plurality of word lines that is adjacent from one another during a predetermined charging time, and that generates a short sense signal that indicates whether short between adjacent word lines is occurred by checking voltage levels of the word lines that were supplied with a same level of voltage, after the charging time is lapsed by a predetermined time.
摘要翻译：公开了一种使用字线缺陷检查电路设置在其中的非易失性半导体存储器件。非易失性半导体存储器件包括：包括多个单元阵列块的存储单元阵列，所述多个单元阵列块包括由浮置栅极存储单元晶体管组成的多个单元串，所述浮栅存储单元晶体管的漏源通道在串选择晶体管之间串联连接和地选择晶体管，并且其控制栅极对应地连接到多个字线，以及字线短路检查电路，其在预定充电期间彼此相邻的多个字线中的每一个输入不同电平的电压并且在充电时间经过预定时间之后，通过检查提供有相同电平电平的字线的电压电平，产生指示相邻字线之间是否发生短路的短路检测信号。

10. 发明授权

US07852682B2 Flash memory device and program method of flash memory device using different voltages 有权
标题翻译：闪存器件和使用不同电压的闪存器件的程序方法
公开(公告)号：US07852682B2
公开(公告)日：2010-12-14
申请号：US11830260
申请日：2007-07-30
申请人： Dae-Seok Byeon , Young-Ho Lim
发明人： Dae-Seok Byeon , Young-Ho Lim
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/10
摘要： A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.
摘要翻译：闪速存储器和闪速存储器的编程方法包括对字线施加通过电压以升高被释放到接地电压的通道电压。一个编程电压被施加到所选择的字线，并且当编程电压被施加到所选择的字线时，局部电压被施加到提供有通过电压的至少一个字线。局部电压低于通过电压，等于或高于接地电压。在将编程电压施加到所选择的字线之前，升压的通道电压可以被放电。

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