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1. 发明授权

US09026882B2 Semiconductor device and method of writing data to semiconductor device 有权
标题翻译：半导体器件及将数据写入半导体器件的方法
公开(公告)号：US09026882B2
公开(公告)日：2015-05-05
申请号：US13523969
申请日：2012-06-15
申请人： Daisuke Oshida , Shigeru Furuta , Masayuki Hirokawa , Akira Yamazaki , Takashi Fujimori , Shigemasa Shiota
发明人： Daisuke Oshida , Shigeru Furuta , Masayuki Hirokawa , Akira Yamazaki , Takashi Fujimori , Shigemasa Shiota
IPC分类号： H03M13/00 , H04L9/32
CPC分类号： H04L9/3226 , H03M13/29 , H03M13/63 , H04L9/3278 , H04L2209/04 , H04L2209/08 , H04L2209/34
摘要： A semiconductor device has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information.
摘要翻译：半导体器件具有：唯一代码生成单元，其生成初始唯一代码，其是设备唯一的值，并且包括随机位中的错误; 第一纠错单元，校正所述初始唯一码中的错误以产生中间唯一码; 第二纠错单元，修正中间唯一码中的错误，以产生第一确定唯一码; 以及解密单元，利用所述第一确定唯一代码，通过由外部设备通过基于所述中间特征码产生的密钥信息对机密信息进行加密而获得的传输数据进行解密，以生成机密信息。

2. 发明申请

US20120324241A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120324241A1
公开(公告)日：2012-12-20
申请号：US13524000
申请日：2012-06-15
申请人： Daisuke OSHIDA , Masayuki Hirokawa , Akira Yamazaki , Takashi Fujimori , Shigemasa Shiota , Shigeru Furuta
发明人： Daisuke OSHIDA , Masayuki Hirokawa , Akira Yamazaki , Takashi Fujimori , Shigemasa Shiota , Shigeru Furuta
IPC分类号： G06F12/14
CPC分类号： G06F21/78 , G06F12/1408 , G06F21/72 , G06F21/73 , G06F21/79 , G06F2221/2107 , G06F2221/2129 , G09C1/00 , H04L9/002 , H04L9/0866 , H04L2209/08 , H04L2209/12
摘要： A semiconductor device in related art has a problem that security on confidential information stored is insufficient. A semiconductor device of the present invention has a unique code which is unique to a device and generates unique code corresponding information from the unique code. The semiconductor device has a memory region in which specific information obtained by encrypting confidential information is stored in a region associated with the unique code corresponding information. The specific information read from the memory region is encrypted with the unique code corresponding information to generate the confidential information.
摘要翻译：相关技术的半导体装置存在存储的机密信息的安全性不足的问题。本发明的半导体器件具有唯一的代码，该代码对于器件是唯一的，并且从唯一代码生成唯一代码对应的信息。半导体器件具有其中通过加密机密信息获得的特定信息被存储在与唯一代码对应信息相关联的区域中的存储区域。从存储器区域读取的特定信息用唯一的代码对应信息加密以生成机密信息。

3. 发明授权

US08782432B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08782432B2
公开(公告)日：2014-07-15
申请号：US13524000
申请日：2012-06-15
申请人： Daisuke Oshida , Masayuki Hirokawa , Akira Yamazaki , Takashi Fujimori , Shigemasa Shiota , Shigeru Furuta
发明人： Daisuke Oshida , Masayuki Hirokawa , Akira Yamazaki , Takashi Fujimori , Shigemasa Shiota , Shigeru Furuta
IPC分类号： G06F11/30 , H04L9/08 , G06F21/73 , G06F21/79 , G06F12/14 , H04L9/00
CPC分类号： G06F21/78 , G06F12/1408 , G06F21/72 , G06F21/73 , G06F21/79 , G06F2221/2107 , G06F2221/2129 , G09C1/00 , H04L9/002 , H04L9/0866 , H04L2209/08 , H04L2209/12
摘要： A semiconductor device in related art has a problem that security on confidential information stored is insufficient. A semiconductor device of the present invention has a unique code which is unique to a device and generates unique code corresponding information from the unique code. The semiconductor device has a memory region in which specific information obtained by encrypting confidential information is stored in a region associated with the unique code corresponding information. The specific information read from the memory region is encrypted with the unique code corresponding information to generate the confidential information.
摘要翻译：相关技术的半导体装置存在存储的机密信息的安全性不足的问题。本发明的半导体器件具有唯一的代码，该代码对于器件是唯一的，并且从唯一代码生成唯一代码对应的信息。半导体器件具有其中通过加密机密信息获得的特定信息被存储在与唯一代码对应信息相关联的区域中的存储区域。从存储器区域读取的特定信息用唯一的代码对应信息加密以生成机密信息。

4. 发明申请

US20120324310A1 SEMICONDUCTOR DEVICE AND METHOD OF WRITING DATA TO SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及将数据写入半导体器件的方法
公开(公告)号：US20120324310A1
公开(公告)日：2012-12-20
申请号：US13523969
申请日：2012-06-15
申请人： Daisuke OSHIDA , Shigeru Furuta , Masayuki Hirokawa , Akira Yamazaki , Takashi Fujimori , Shigemasa Shiota
发明人： Daisuke OSHIDA , Shigeru Furuta , Masayuki Hirokawa , Akira Yamazaki , Takashi Fujimori , Shigemasa Shiota
IPC分类号： H03M13/29 , G06F21/24 , G06F11/10
CPC分类号： H04L9/3226 , H03M13/29 , H03M13/63 , H04L9/3278 , H04L2209/04 , H04L2209/08 , H04L2209/34
摘要： A semiconductor device in related art has a problem that security at the time of writing data cannot be sufficiently assured. A semiconductor device of the present invention has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information.
摘要翻译：相关技术的半导体器件具有无法充分确保写入数据时的安全性的问题。本发明的半导体器件具有：唯一代码生成单元，其生成初始唯一代码，其是设备唯一的值，并且包括随机位中的错误; 第一纠错单元，校正所述初始唯一码中的错误以产生中间唯一码; 第二纠错单元，修正中间唯一码中的错误，以产生第一确定唯一码; 以及解密单元，利用所述第一确定唯一代码，通过由外部设备通过基于所述中间特征码产生的密钥信息对机密信息进行加密而获得的传输数据进行解密，以生成机密信息。

5. 发明授权

US09363082B2 Cryptographic communication system and cryptographic communication method 有权
标题翻译：密码通信系统和密码通信方式
公开(公告)号：US09363082B2
公开(公告)日：2016-06-07
申请号：US13495064
申请日：2012-06-13
申请人： Shigemasa Shiota , Shigeru Furuta , Masayuki Hirokawa , Akira Yamazaki , Daisuke Oshida
发明人： Shigemasa Shiota , Shigeru Furuta , Masayuki Hirokawa , Akira Yamazaki , Daisuke Oshida
IPC分类号： H04L29/06 , H04L9/30 , H04L9/08 , H04L9/32
CPC分类号： H04L9/0861 , H04L9/0822 , H04L9/0866 , H04L9/0869 , H04L9/14 , H04L9/30 , H04L9/304 , H04L9/3247 , H04L9/3278 , H04L2209/04 , H04L2209/24 , H04L2209/34 , H04L2209/80 , H04L2209/84
摘要： Provided is a cryptographic communication system including a first semiconductor device and a second semiconductor device. The first semiconductor device includes a common key generation unit that generates a common key CK(a) by using a unique code UC(a) and correction data CD(a), and an encryption unit that encrypts the common key CK(a) generated in the common key generation unit by using a public key PK(b) of the second semiconductor device. The second semiconductor device includes a secret key generation unit that generates a secret key SK(b) by using a unique code UC(b) and correction data CD(b), and a decryption unit that decrypts the common key CK(a) encrypted in the encryption unit by using the secret key SK(b).
摘要翻译：提供了包括第一半导体器件和第二半导体器件的密码通信系统。第一半导体装置包括通过使用唯一码UC（a）和校正数据CD（a）来生成公共密钥CK（a）的公共密钥生成单元，以及对生成的公共密钥CK（a）进行加密的加密单元通过使用第二半导体器件的公开密钥PK（b）在公共密钥生成单元中。第二半导体装置包括通过使用唯一码UC（b）和校正数据CD（b）来生成秘密密钥SK（b）的秘密密钥生成单元，以及解密单元，对公共密钥CK（a）进行加密在密码单元中使用秘密密钥SK（b）。

6. 再颁专利

USRE45857E1 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：USRE45857E1
公开(公告)日：2016-01-19
申请号：US13475679
申请日：2012-05-18
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译：一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统，对连续扇区数据的读命令作出响应。

7. 发明授权

US08064257B2 Semiconductor memory device having faulty cells 有权
标题翻译：具有故障单元的半导体存储器件
公开(公告)号：US08064257B2
公开(公告)日：2011-11-22
申请号：US12615502
申请日：2009-11-10
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C11/34
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

8. 发明申请

US20100257313A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100257313A1
公开(公告)日：2010-10-07
申请号：US12303110
申请日：2007-05-16
申请人： Hirotaka Nishizawa , Junichiro Osako , Minoru Shinohara , Tamaki Wada , Kunihirio Katayama , Shigemasa Shiota
发明人： Hirotaka Nishizawa , Junichiro Osako , Minoru Shinohara , Tamaki Wada , Kunihirio Katayama , Shigemasa Shiota
IPC分类号： G06F12/00 , G06F1/32 , G06F1/26
CPC分类号： G06K19/077 , G06K19/0719 , G06K19/072
摘要： A semiconductor device has operation modes selectable through the control by a second microcomputer (113). In a first mode, an operation of a memory controller (105) responding to a memory card command from a memory card interface terminal and an operation of a first microcomputer (106) responding to an IC card command from an IC card interface terminal are separately performed. In a second mode, the first microcomputer operates in response to the IC card command from the IC card interface terminal. In a third mode, the memory controller and the first microcomputer operate in response to an undefined IC card command from the IC card interface terminal. In a fourth mode, the memory controller and the first microcomputer operate in response to the memory card command from the memory card interface terminal. Convenience of the semiconductor device having an IC card function and a memory card function is improved.
摘要翻译：半导体器件具有通过第二微型计算机（113）的控制可选择的操作模式。在第一模式中，分别响应来自存储卡接口终端的存储卡命令的存储器控制器（105）的操作和来自IC卡接口终端的响应IC卡命令的第一微计算机（106）的操作执行。在第二模式中，第一微型计算机响应于来自IC卡接口终端的IC卡命令而工作。在第三模式中，存储器控制器和第一微型计算机响应于来自IC卡接口终端的未定义的IC卡命令来操作。在第四模式中，存储器控制器和第一微型计算机响应来自存储卡接口终端的存储卡命令而操作。提高具有IC卡功能和存储卡功能的半导体器件的便利性。

9. 发明申请

US20100054069A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20100054069A1
公开(公告)日：2010-03-04
申请号：US12251444
申请日：2008-10-14
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Yasuhiro Nakamura
IPC分类号： G11C7/00
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译：本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行时间分享的方式。

10. 发明申请

US20080229164A1 MEMORY CARD AND MEMORY CONTROLLER 失效
标题翻译：内存卡和内存控制器
公开(公告)号：US20080229164A1
公开(公告)日：2008-09-18
申请号：US12125042
申请日：2008-05-21
申请人： Takayuki TAMURA , Hirofumi Shibuya , Hiroyuki Goto , Shigemasa Shiota , Yasuhiro Nakamura
发明人： Takayuki TAMURA , Hirofumi Shibuya , Hiroyuki Goto , Shigemasa Shiota , Yasuhiro Nakamura
IPC分类号： G11C29/00
CPC分类号： G06F11/1068
摘要： A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.
摘要翻译：存储卡包括非易失性存储器，用于控制存储卡的操作的存储器控制器。存储器控制器能够根据预定协议向外部提供接口，并且以规定的时间间隔或在电力供应连接的定时执行存储器信息的错误检测和校正，而不依赖于读出存储器信息到外部访问请求。因此，无需主机装置从存储卡的非易失性存储器中读出存储器信息，可以提高非易失性存储器中的数据保持的可靠性。

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