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1. 发明申请

US20130111130A1 MEMORY INCLUDING A REDUCED LEAKAGE WORDLINE DRIVER 有权
标题翻译：内存包括减少字幕驱动程序
公开(公告)号：US20130111130A1
公开(公告)日：2013-05-02
申请号：US13286351
申请日：2011-11-01
申请人： Edward M. McCombs , Stephen C. Horne , Alexander E. Runas , Daniel C. Chow
发明人： Edward M. McCombs , Stephen C. Horne , Alexander E. Runas , Daniel C. Chow
IPC分类号： G11C5/14 , G06F12/08
CPC分类号： G11C8/08
摘要： A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.
摘要翻译：存储器包括具有减少的泄漏的字线驱动器。存储器包括耦合到第一电压源的存储阵列以及包括驱动器反相器的多个字线驱动器单元。在低功率模式期间，耦合到字线电路的电压源的电压被减小或去除，而耦合到存储阵列的电压源的电压至少保持在保持电压。此外，p型晶体管耦合在阵列电压源和字线驱动器反相器的输入之间，从而将字线驱动器反相器的输出保持在低逻辑电平以防止意外的字线触发。

2. 发明授权

US08837226B2 Memory including a reduced leakage wordline driver 有权
标题翻译：存储器包括减少泄漏字线驱动器
公开(公告)号：US08837226B2
公开(公告)日：2014-09-16
申请号：US13286351
申请日：2011-11-01
申请人： Edward M. McCombs , Stephen C. Horne , Alexander E. Runas , Daniel C. Chow
发明人： Edward M. McCombs , Stephen C. Horne , Alexander E. Runas , Daniel C. Chow
IPC分类号： G11C11/34 , G11C8/08
CPC分类号： G11C8/08
摘要： A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.
摘要翻译：存储器包括具有减少泄漏的字线驱动器。存储器包括耦合到第一电压源的存储阵列以及包括驱动器反相器的多个字线驱动器单元。在低功率模式期间，耦合到字线电路的电压源的电压被减小或去除，而耦合到存储阵列的电压源的电压至少保持在保持电压。此外，p型晶体管耦合在阵列电压源和字线驱动器反相器的输入之间，从而将字线驱动器反相器的输出保持在低逻辑电平以防止意外的字线触发。

3. 发明授权

US08553472B2 Memory with a shared I/O including an output data latch having an integrated clamp 有权
标题翻译：具有共享I / O的存储器，包括具有集成钳位的输出数据锁存器
公开(公告)号：US08553472B2
公开(公告)日：2013-10-08
申请号：US13311340
申请日：2011-12-05
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/106
摘要： A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.
摘要翻译：存储器包括在多个存储阵列之间共享的共享I / O单元，提供来自阵列的输出数据。共享I / O包括具有集成输出钳位的输出锁存器。 I / O单元可以被配置为经由数据输出信号路径从存储阵列提供输出数据。 I / O单元包括输出锁存器，其被配置为响应于掉电状态来迫使数据输出信号路径上的有效逻辑电平。

4. 发明申请

US20130188435A1 MEMORY HAVING ISOLATION UNITS FOR ISOLATING STORAGE ARRAYS FROM A SHARED I/O DURING RETENTION MODE OPERATION 有权
标题翻译：在保留模式操作期间从分享的I / O分离存储阵列的隔离单元的内存
公开(公告)号：US20130188435A1
公开(公告)日：2013-07-25
申请号：US13356786
申请日：2012-01-24
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/06 , G11C7/10
CPC分类号： G11C5/063 , G11C7/06 , G11C11/4091 , G11C2207/002
摘要： A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.
摘要翻译：存储器包括在多个存储阵列之间共享的I / O单元。共享I / O单元提供阵列的输出数据。存储器包括连接在每个存储阵列和共享I / O单元之间的隔离单元。此外，每个存储阵列和共享I / O单元可以通过例如电源门控电路连接到单独的开关电压域。如果一个或多个存储阵列被置于保持或低电压模式，则耦合到受影响的存储阵列的隔离单元可以被配置为将这些存储阵列的位线与共享的I / O数据路径隔离开来。

5. 发明申请

US20120134225A1 SENSE AMPLIFIER LATCH WITH INTEGRATED TEST DATA MULTIPLEXER 有权
标题翻译：具有集成测试数据多路复用器的感应放大器插座
公开(公告)号：US20120134225A1
公开(公告)日：2012-05-31
申请号：US13212450
申请日：2011-08-18
申请人： Daniel C. Chow
发明人： Daniel C. Chow
IPC分类号： G11C7/06
CPC分类号： G11C7/08 , G11C29/48
摘要： A sense amplifier latch may be provided to controllably latch the output of a sense amplifier. The latch may open in response to assertion of a latch enable signal to receive data, and close in response to deassertion of the latch enable signal to capture and store the received data. Additionally, a multiplexer may be provided to select from among multiple sources of test data, such as scan data and bypass data. The multiplexer may produce a test data input to the sense amplifier latch that encodes a data value and a control value that causes the data value to be selected. Depending on the state of the test data input, the sense amplifier latch may output either a value received from the sense amplifier or a value encoded in the test data input.
摘要翻译：可以提供读出放大器锁存器以可控制地锁存读出放大器的输出。响应于锁存使能信号的断言来接收数据，锁存器可以打开，并且响应于锁存使能信号的取消取消而关闭以捕获和存储所接收的数据。另外，可以提供多路复用器以从多个测试数据源中选择，例如扫描数据和旁路数据。复用器可以产生输入到读出放大器锁存器的测试数据，该读取放大器锁存器对数据值进行编码，并且控制值可以使数据值被选择。根据测试数据输入的状态，读出放大器锁存器可以输出从读出放大器接收的值或在测试数据输入中编码的值。

6. 发明授权

US08570824B2 Memory having isolation units for isolating storage arrays from a shared I/O during retention mode operation 有权
标题翻译：存储器具有隔离单元，用于在保持模式操作期间将存储阵列与共享I / O隔离
公开(公告)号：US08570824B2
公开(公告)日：2013-10-29
申请号：US13356786
申请日：2012-01-24
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/02
CPC分类号： G11C5/063 , G11C7/06 , G11C11/4091 , G11C2207/002
摘要： A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.
摘要翻译：存储器包括在多个存储阵列之间共享的I / O单元。共享I / O单元提供阵列的输出数据。存储器包括连接在每个存储阵列和共享I / O单元之间的隔离单元。此外，每个存储阵列和共享I / O单元可以通过例如电源门控电路连接到单独的开关电压域。如果一个或多个存储阵列被置于保持或低电压模式，则耦合到受影响的存储阵列的隔离单元可以被配置为将这些存储阵列的位线与共享的I / O数据路径隔离开来。

7. 发明授权

US08553481B2 Sense amplifier latch with integrated test data multiplexer 有权
标题翻译：带集成测试数据多路复用器的感应放大器锁存器
公开(公告)号：US08553481B2
公开(公告)日：2013-10-08
申请号：US13212450
申请日：2011-08-18
申请人： Daniel C. Chow
发明人： Daniel C. Chow
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C29/48
摘要： A sense amplifier latch may be provided to controllably latch the output of a sense amplifier. The latch may open in response to assertion of a latch enable signal to receive data, and close in response to deassertion of the latch enable signal to capture and store the received data. Additionally, a multiplexer may be provided to select from among multiple sources of test data, such as scan data and bypass data. The multiplexer may produce a test data input to the sense amplifier latch that encodes a data value and a control value that causes the data value to be selected. Depending on the state of the test data input, the sense amplifier latch may output either a value received from the sense amplifier or a value encoded in the test data input.
摘要翻译：可以提供读出放大器锁存器以可控制地锁存读出放大器的输出。响应于锁存使能信号的断言来接收数据，锁存器可以打开，并且响应于锁存使能信号的取消取消而关闭以捕获和存储所接收的数据。另外，可以提供多路复用器以从多个测试数据源中选择，例如扫描数据和旁路数据。复用器可以产生输入到读出放大器锁存器的测试数据，该读取放大器锁存器对数据值进行编码，并且控制值可以使数据值被选择。根据测试数据输入的状态，读出放大器锁存器可以输出从读出放大器接收的值或在测试数据输入中编码的值。

8. 发明申请

US20120134226A1 SENSE AMPLIFIER AND SENSE AMPLIFIER LATCH HAVING COMMON CONTROL 有权
标题翻译： SENSE放大器和SENSE放大器LATCH具有共同控制
公开(公告)号：US20120134226A1
公开(公告)日：2012-05-31
申请号：US13212490
申请日：2011-08-18
申请人： Daniel C. Chow
发明人： Daniel C. Chow
IPC分类号： G11C7/06
CPC分类号： G11C7/08 , G11C29/48
摘要： A sense amplifier of a memory array may be provided to amplify data presented from storage cells of the memory array. Additionally, a sense amplifier latch may be provided to store data received from the sense amplifier. The sense amplifier may be enabled for operation by a sense amplifier enable signal that is distinct from a clock signal. Moreover, the latch enable signal of the sense amplifier latch may be controlled by the sense amplifier enable signal, such that the sense amplifier latch opens in response to activation of the sense amplifier and closes in response to deactivation of the sense amplifier.
摘要翻译：可以提供存储器阵列的读出放大器来放大从存储器阵列的存储单元呈现的数据。此外，可以提供读出放大器锁存器来存储从读出放大器接收的数据。可以通过与时钟信号不同的读出放大器使能信号来使读出放大器工作。此外，读出放大器锁存器的锁存使能信号可以由读出放大器使能信号来控制，使得读出放大器锁存器响应于感测放大器的激活而打开，并响应于读出放大器的去激活而闭合。

9. 发明授权

US08553482B2 Sense amplifier and sense amplifier latch having common control 有权
标题翻译：感应放大器和读出放大器锁存器具有共同的控制
公开(公告)号：US08553482B2
公开(公告)日：2013-10-08
申请号：US13212490
申请日：2011-08-18
申请人： Daniel C. Chow
发明人： Daniel C. Chow
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C29/48
摘要： A sense amplifier of a memory array may be provided to amplify data presented from storage cells of the memory array. Additionally, a sense amplifier latch may be provided to store data received from the sense amplifier. The sense amplifier may be enabled for operation by a sense amplifier enable signal that is distinct from a clock signal. Moreover, the latch enable signal of the sense amplifier latch may be controlled by the sense amplifier enable signal, such that the sense amplifier latch opens in response to activation of the sense amplifier and closes in response to deactivation of the sense amplifier.
摘要翻译：可以提供存储器阵列的读出放大器来放大从存储器阵列的存储单元呈现的数据。此外，可以提供读出放大器锁存器来存储从读出放大器接收的数据。可以通过与时钟信号不同的读出放大器使能信号来使读出放大器工作。此外，读出放大器锁存器的锁存使能信号可以由读出放大器使能信号来控制，使得读出放大器锁存器响应于感测放大器的激活而打开，并响应于读出放大器的去激活而闭合。

10. 发明申请

US20130141988A1 MEMORY WITH A SHARED I/O INCLUDING AN OUTPUT DATA LATCH HAVING AN INTEGRATED CLAMP 有权
标题翻译：具有共享I / O的存储器，包括具有集成钳位的输出数据线
公开(公告)号：US20130141988A1
公开(公告)日：2013-06-06
申请号：US13311340
申请日：2011-12-05
申请人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
发明人： Edward M. McCombs , Daniel C. Chow , Kenneth W. Jones , Alexander E. Runas
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/106
摘要： A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.
摘要翻译：存储器包括在多个存储阵列之间共享的共享I / O单元，提供来自阵列的输出数据。共享I / O包括具有集成输出钳位的输出锁存器。 I / O单元可以被配置为经由数据输出信号路径从存储阵列提供输出数据。 I / O单元包括输出锁存器，其被配置为响应于掉电状态来迫使数据输出信号路径上的有效逻辑电平。

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