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1. 发明申请

US20230140611A1 METHODS, SYSTEMS, APPARATUSES, AND DEVICES FOR FACILITATING SIMULATING GOLF PLAY ON GOLF COURSES 有权
公开(公告)号：US20230140611A1
公开(公告)日：2023-05-04
申请号：US17740993
申请日：2022-05-10
申请人： Daniel D'Souza , Alexandria D'Souza
发明人： Daniel D'Souza , Alexandria D'Souza
IPC分类号： A63B71/06 , A63B69/36 , A63B69/00 , A63B24/00
摘要： Disclosed herein is an apparatus for facilitating simulating golf play on golf courses. Further, the apparatus comprises a golf mat, a golf ball, an external sensor, a processing device, a storage device, and a communication device. Further, an internal sensor diposed in the golf ball generates internal sensor data based on detecting a striking parameter of a striking of the golf ball. Further, the external sensor generates external sensor data based on detecting a motion parameter of a motion of the golf ball. Further, the processing device analyzes the internal sensor data and the external sensor data, generates a path parameter of a path of the golf ball, and generates a representation of the golf ball and the path in an environment representation of a golf course based on the path parameter and golf course data. Further, the storage device retrieves the golf course data.

2. 发明授权

US5254942A Single chip IC tester architecture 失效
标题翻译：单片IC测试仪架构
公开(公告)号：US5254942A
公开(公告)日：1993-10-19
申请号：US894819
申请日：1992-06-08
申请人： Daniel D'Souza , Ruth Alexander
发明人： Daniel D'Souza , Ruth Alexander
IPC分类号： G01R31/3185 , G01R31/3187 , G01R31/319 , G01R31/28
CPC分类号： G01R31/3187 , G01R31/31858 , G01R31/318552 , G01R31/319 , G06F2201/83
摘要： An integrated circuit (IC) test architecture and technique which can be used in conformity with the IEEE 1149.1 test standard and configured on a single chip. This chip can be remotely controlled via a PC or workstation to generate stimulus and collect response data to fully test an IC which matches the foot print of the test chip. The specified technique uses the IEEE test standard with additional logic on a single chip which permits at speed test functional test of ICs. The test chip can be connected to a PC or workstation via the four (4) channel Test Access Port. By remotely controlling the test chip from the PC or Workstation, stimulus and response data can be generated to completely test any Integrated circuit having a foot print matching the IC of the test chip. In one embodiment, the test chip is mounted on a probe card for at speed functional test of wafers. In another embodiment, the test chip is placed in a socket or adapter for at speed package level test. In another embodiment, the test chip is sandwiched between a device under test (DUT) and the PCB on which the DUT is mounted for at speed board test.
摘要翻译：一种集成电路（IC）测试架构和技术，可以使用符合IEEE 1149.1测试标准并在单个芯片上配置。该芯片可以通过PC或工作站进行远程控制，以产生刺激并收集响应数据，以充分测试与测试芯片脚印匹配的IC。指定的技术在单个芯片上使用具有附加逻辑的IEEE测试标准，允许在IC的速度测试功能测试。测试芯片可以通过四（4）个通道测试访问端口连接到PC或工作站。通过从PC或工作站远程控制测试芯片，可以产生刺激和响应数据，以完全测试具有与测试芯片的IC匹配的脚印的任何集成电路。在一个实施例中，测试芯片安装在探针卡上用于晶片的速度功能测试。在另一个实施例中，将测试芯片放置在插座或适配器中以进行速度封装水平测试。在另一个实施例中，测试芯片夹在待测器件（DUT）和安装有DUT的PCB之间用于速度板测试。

3. 发明授权

US5396170A Single chip IC tester architecture 失效
标题翻译：单片IC测试仪架构
公开(公告)号：US5396170A
公开(公告)日：1995-03-07
申请号：US34156
申请日：1993-06-01
申请人： Daniel D'Souza , Ruth Alexander
发明人： Daniel D'Souza , Ruth Alexander
IPC分类号： G01R31/3185 , G01R31/3187 , G01R31/319 , G01R31/28
CPC分类号： G01R31/3187 , G01R31/31858 , G01R31/318552 , G01R31/319 , G06F2201/83
摘要： An integrated circuit (IC) test architecture and technique which can be used in conformity with the IEEE 1149.1 test standard and configured on a single chip. This chip can be remotely controlled via a PC or workstation to generate stimulus and collect response data to fully test an IC which matches the foot print of the test chip. The specified technique uses the IEEE test standard with additional logic on a single chip which permits at speed test functional test of ICs. The test chip can be connected to a PC or workstation via the four (4) channel Test Access Port. By remotely controlling the test chip from the PC or Workstation, stimulus and response data can be generated to completely test any Integrated circuit having a foot print matching the IC of the test chip. In one embodiment, the test chip is mounted on a probe card for at speed functional test of wafers. In another embodiment, the test chip is placed in a socket or adapter for at speed package level test. In another embodiment, the test chip is sandwiched between a device under test (DUT) and the PCB on which the DUT is mounted for at speed board test.
摘要翻译：一种集成电路（IC）测试架构和技术，可以使用符合IEEE 1149.1测试标准并在单个芯片上配置。该芯片可以通过PC或工作站进行远程控制，以产生刺激并收集响应数据，以充分测试与测试芯片脚印匹配的IC。指定的技术在单个芯片上使用具有附加逻辑的IEEE测试标准，允许在IC的速度测试功能测试。测试芯片可以通过四（4）个通道测试访问端口连接到PC或工作站。通过从PC或工作站远程控制测试芯片，可以产生刺激和响应数据，以完全测试具有与测试芯片的IC匹配的脚印的任何集成电路。在一个实施例中，测试芯片安装在探针卡上用于晶片的速度功能测试。在另一个实施例中，将测试芯片放置在插座或适配器中以进行速度封装水平测试。在另一个实施例中，测试芯片夹在待测器件（DUT）和安装有DUT的PCB之间用于速度板测试。

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