专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07453288B2 Clock translator and parallel to serial converter 有权
标题翻译：时钟转换器并行串行转换器
公开(公告)号：US07453288B2
公开(公告)日：2008-11-18
申请号：US11356227
申请日：2006-02-16
申请人： Darrell Eugene Tinker
发明人： Darrell Eugene Tinker
IPC分类号： H03K19/00
CPC分类号： H03M9/00 , G06F1/06
摘要： A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.
摘要翻译：公开了一种使用一个或多个时钟信号的系统和方法。该系统包括时钟转换器，其具有接收第一参考时钟信号的第一输入端和用于接收第二参考时钟信号的第二输入端。时钟转换器还包括一个输出端，以提供相对于第一参考时钟的频率具有第一比率的时钟频率但具有基于第二参考时钟信号的至少一部分的分辨率的比特率时钟信号。第二个参考时钟的速率比第一个参考时钟快。

2. 发明申请

US20110060783A1 DECIMATION FILTER 有权
标题翻译：十进制滤波器
公开(公告)号：US20110060783A1
公开(公告)日：2011-03-10
申请号：US12945259
申请日：2010-11-12
申请人： Darrell Eugene Tinker
发明人： Darrell Eugene Tinker
IPC分类号： G06F17/10 , G06F17/17
CPC分类号： H03H17/0248 , H03H17/0628 , H03H17/0671 , H03H17/0685
摘要： A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module.
摘要翻译：系统包括具有可调节抽取率的抽取模块和响应于抽取模块的滤波模块。数字锁相环可操作以控制抽取模块的抽取率。抽取模块是级联积分梳抽取模块。

3. 发明授权

US07856464B2 Decimation filter 有权
标题翻译：抽取滤波器
公开(公告)号：US07856464B2
公开(公告)日：2010-12-21
申请号：US11356338
申请日：2006-02-16
申请人： Darrell Eugene Tinker
发明人： Darrell Eugene Tinker
IPC分类号： G06F17/10 , G06F17/17 , G06F7/38 , H03M7/00
CPC分类号： H03H17/0248 , H03H17/0628 , H03H17/0671 , H03H17/0685
摘要： A system and method for decimating a digital signal is disclosed. The system includes an input to receive digital data, a control input to receive a desired decimation rate, and an integrator stage responsive to the input. The system also includes a variable rate down sampling module responsive to the integrator stage and a differentiator stage responsive to the variable rate down sampling module. The down sampling module has a decimation rate that is dynamically adjustable based on the desired decimation rate.
摘要翻译：公开了一种用于抽取数字信号的系统和方法。该系统包括用于接收数字数据的输入，用于接收期望的抽取率的控制输入和响应于该输入的积分器级。该系统还包括响应于积分器级的可变降速采样模块和响应于可变速率下降采样模块的微分器级。下采样模块具有基于所需抽取速率动态调节的抽取率。

4. 发明授权

US07724861B2 Sample rate converter 有权
标题翻译：采样率转换器
公开(公告)号：US07724861B2
公开(公告)日：2010-05-25
申请号：US11386873
申请日：2006-03-22
申请人： Darrell Eugene Tinker
发明人： Darrell Eugene Tinker
IPC分类号： H03D3/24
CPC分类号： H03H17/0628
摘要： A system and method for determining a clock rate of a digital phase lock loop is disclosed. The system includes a first input to receive a first clock signal, an output to provide a second clock signal, and a dividerless initial clock rate determination module to calculate an initial clock rate value based on an reciprocal of a pulse length of the first clock signal. In a particular embodiment, the dividerless initial clock rate determination module performs a piecewise linear operation to calculate the initial clock rate value.
摘要翻译：公开了一种用于确定数字锁相环的时钟速率的系统和方法。该系统包括用于接收第一时钟信号的第一输入端，用于提供第二时钟信号的输出端和无分频器初始时钟速率确定模块，用于基于第一时钟信号的脉冲长度的倒数来计算初始时钟速率值。在特定实施例中，无分频器初始时钟速率确定模块执行分段线性运算以计算初始时钟速率值。

5. 发明授权

US08635261B2 Decimation filter 有权
标题翻译：抽取滤波器
公开(公告)号：US08635261B2
公开(公告)日：2014-01-21
申请号：US12945259
申请日：2010-11-12
申请人： Darrell Eugene Tinker
发明人： Darrell Eugene Tinker
IPC分类号： G06F17/17 , H03M7/00
CPC分类号： H03H17/0248 , H03H17/0628 , H03H17/0671 , H03H17/0685
摘要： A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module.
摘要翻译：系统包括具有可调节抽取率的抽取模块和响应于抽取模块的滤波模块。数字锁相环可操作以控制抽取模块的抽取率。抽取模块是级联积分梳抽取模块。

6. 发明授权

US07773006B2 Systems and methods of parallel to serial conversion 有权
标题翻译：与串行转换并行的系统和方法
公开(公告)号：US07773006B2
公开(公告)日：2010-08-10
申请号：US12250027
申请日：2008-10-13
申请人： Darrell Eugene Tinker
发明人： Darrell Eugene Tinker
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , G06F1/06
摘要： A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.
摘要翻译：公开了一种使用一个或多个时钟信号的系统和方法。该系统包括具有用于接收第一参考时钟信号的第一输入和接收第二参考时钟信号的第二输入的时钟转换器。时钟转换器还包括一个输出端，以提供相对于第一参考时钟的频率具有第一比率的时钟频率但具有基于第二参考时钟信号的至少一部分的分辨率的比特率时钟信号。第二个参考时钟的速率比第一个参考时钟快。

7. 发明申请

US20090033527A1 Systems and Methods of Parallel to Serial Conversion 有权
标题翻译：并行到串行转换的系统和方法
公开(公告)号：US20090033527A1
公开(公告)日：2009-02-05
申请号：US12250027
申请日：2008-10-13
申请人： Darrell Eugene Tinker
发明人： Darrell Eugene Tinker
IPC分类号： H03M7/32 , H03M9/00
CPC分类号： H03M9/00 , G06F1/06
摘要： A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.
摘要翻译：公开了一种使用一个或多个时钟信号的系统和方法。该系统包括具有用于接收第一参考时钟信号的第一输入和接收第二参考时钟信号的第二输入的时钟转换器。时钟转换器还包括一个输出端，以提供相对于第一参考时钟的频率具有第一比率的时钟频率但具有基于第二参考时钟信号的至少一部分的分辨率的比特率时钟信号。第二个参考时钟的速率比第一个参考时钟快。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式