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1. 发明申请

US20120182787A1 CROSS-POINT MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING CROSS-POINT MEMORY DEVICES AND METHODS OF ACCESSING A PLURALITY OF MEMORY CELLS IN A CROSS-POINT MEMORY ARRAY 有权
标题翻译：跨点存储器件，包括跨点存储器件的电子系统和在一个十字形存储器阵列中存取大量存储器单元的方法
公开(公告)号：US20120182787A1
公开(公告)日：2012-07-19
申请号：US13430970
申请日：2012-03-27
申请人： David H. Wells , Jun Liu
发明人： David H. Wells , Jun Liu
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C8/10 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C2013/0054
摘要： Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.
摘要翻译：存储器件包括多个存储器单元，每个存储器单元包括存储元件和选择器件。多个第一（例如，行）地址线可以在多个的至少一些单元的第一侧相邻（例如，在下方）。多个第二（例如，列）地址线跨越多个行地址线延伸，每个列地址线在至少一些单元的第二相对侧相邻（例如，在上）。控制电路可以被配置为基本上同时向地址线施加读取电压或写入电压。还公开了包括这种存储器件的系统和至少基本上同时访问多个单元的方法。

2. 发明授权

US09673102B2 Methods of forming vertical field-effect transistor with self-aligned contacts for memory devices with planar periphery/array and intermediate structures formed thereby 有权
公开(公告)号：US09673102B2
公开(公告)日：2017-06-06
申请号：US13078274
申请日：2011-04-01
申请人： Jun Liu , Sanh D. Tang , David H. Wells
发明人： Jun Liu , Sanh D. Tang , David H. Wells
IPC分类号： H01L21/8234 , H01L27/24 , H01L29/66 , H01L29/78 , H01L27/105 , H01L45/00
CPC分类号： H01L27/2454 , H01L21/823487 , H01L27/105 , H01L27/2463 , H01L29/45 , H01L29/665 , H01L29/66666 , H01L29/7827 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.

3. 发明授权

US09025370B2 Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array 有权
标题翻译：交叉点存储器件，包括交叉点存储器件的电子系统和访问交叉点存储器阵列中的多个存储器单元的方法
公开(公告)号：US09025370B2
公开(公告)日：2015-05-05
申请号：US13430970
申请日：2012-03-27
申请人： David H. Wells , Jun Liu
发明人： David H. Wells , Jun Liu
IPC分类号： G11C11/14 , G11C11/16 , G11C5/02 , G11C8/10
CPC分类号： G11C13/0069 , G11C5/02 , G11C8/10 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C2013/0054
摘要： Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.
摘要翻译：存储器件包括多个存储器单元，每个存储器单元包括存储元件和选择器件。多个第一（例如，行）地址线可以在多个的至少一些单元的第一侧相邻（例如，在下方）。多个第二（例如，列）地址线跨越多个行地址线延伸，每个列地址线在至少一些单元的第二相对侧相邻（例如，在上）。控制电路可以被配置为基本上同时向地址线施加读取电压或写入电压。还公开了包括这种存储器件的系统和至少基本上同时访问多个单元的方法。

4. 发明申请

US20100321988A1 CROSS-POINT MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING CROSS-POINT MEMORY DEVICES AND METHODS OF ACCESSING A PLURALITY OF MEMORY CELLS IN A CROSS-POINT MEMORY ARRAY 有权
标题翻译：跨点存储器件，包括跨点存储器件的电子系统和在一个十字形存储器阵列中存取大量存储器单元的方法
公开(公告)号：US20100321988A1
公开(公告)日：2010-12-23
申请号：US12489605
申请日：2009-06-23
申请人： David H. Wells , Jun Liu
发明人： David H. Wells , Jun Liu
IPC分类号： G11C11/00 , G11C7/10 , G11C8/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C8/10 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C2013/0054
摘要： Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.
摘要翻译：存储器件包括多个存储器单元，每个存储器单元包括存储元件和选择器件。多个第一（例如，行）地址线可以在多个的至少一些单元的第一侧相邻（例如，在下方）。多个第二（例如，列）地址线跨越多个行地址线延伸，每个列地址线在至少一些单元的第二相对侧相邻（例如，在上）。控制电路可以被配置为基本上同时向地址线施加读取电压或写入电压。还公开了包括这种存储器件的系统和至少基本上同时访问多个单元的方法。

5. 发明授权

US08144506B2 Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array 有权
标题翻译：交叉点存储器件，包括交叉点存储器件的电子系统和访问交叉点存储器阵列中的多个存储器单元的方法
公开(公告)号：US08144506B2
公开(公告)日：2012-03-27
申请号：US12489605
申请日：2009-06-23
申请人： David H. Wells , Jun Liu
发明人： David H. Wells , Jun Liu
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C8/10 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C2013/0054
摘要： Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.
摘要翻译：存储器件包括多个存储器单元，每个存储器单元包括存储元件和选择器件。多个第一（例如，行）地址线可以在多个的至少一些单元的第一侧相邻（例如，在下方）。多个第二（例如，列）地址线跨越多个行地址线延伸，每个列地址线在至少一些单元的第二相对侧相邻（例如，在上）。控制电路可以被配置为基本上同时向地址线施加读取电压或写入电压。还公开了包括这种存储器件的系统和至少基本上同时访问多个单元的方法。

6. 发明申请

US20120248529A1 METHODS OF FORMING VERTICAL FIELD-EFFECT TRANSISTOR WITH SELF-ALIGNED CONTACTS FOR MEMORY DEVICES WITH PLANAR PERIPHERY/ARRAY AND INTERMEDIATE STRUCTURES FORMED THEREBY 有权
标题翻译：用于具有平面外围/阵列的存储器件的自对准接触件形成垂直场效应晶体管的方法和形成的中间结构
公开(公告)号：US20120248529A1
公开(公告)日：2012-10-04
申请号：US13078274
申请日：2011-04-01
申请人： Jun Liu , Sanh D. Tang , David H. Wells
发明人： Jun Liu , Sanh D. Tang , David H. Wells
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/2454 , H01L21/823487 , H01L27/105 , H01L27/2463 , H01L29/45 , H01L29/665 , H01L29/66666 , H01L29/7827 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.
摘要翻译：形成具有包括多个阵列晶体管的阵列部分和包括存储器件的外围电路晶体管结构的周边区域的存储器件的方法，其中外围区域的上表面和阵列部分的上表面是平面的（或在形成外围电路晶体管结构和多个存储单元（形成在阵列晶体管上）之后，几乎是平面的）。该方法包括在外围区域中形成外围电路晶体管结构，在阵列部分中形成多个阵列晶体管，并在各个垂直晶体管上形成多个存储单元。通过该方法形成的结构具有外围和阵列区域的平面上表面。

7. 发明授权

US08791447B2 Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells 有权
标题翻译：非易失性存储单元的阵列和形成非易失性存储单元阵列的方法
公开(公告)号：US08791447B2
公开(公告)日：2014-07-29
申请号：US13010048
申请日：2011-01-20
申请人： Zengtao T. Liu , David H. Wells
发明人： Zengtao T. Liu , David H. Wells
IPC分类号： H01L29/06
CPC分类号： H01L27/2409 , G11C5/02 , H01L27/249 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/145 , H01L45/146 , H01L45/147
摘要： A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and second electrodes. Current conductive material is in series between and with the programmable material and the select device. An array of vertically stacked tiers of such nonvolatile memory cells is disclosed. Methods of forming arrays of nonvolatile memory cells are disclosed.
摘要翻译：非易失性存储单元包括第一和第二电极。可编程材料和选择装置被串联接纳在第一和第二电极之间。当前导电材料与可编程材料和选择装置之间串联在一起。公开了这种非易失性存储单元的垂直层叠的阵列。公开了形成非易失性存储单元阵列的方法。

8. 发明申请

US20130069030A1 RESISTIVE MEMORY CELL INCLUDING INTEGRATED SELECT DEVICE AND STORAGE ELEMENT 有权
标题翻译：电阻式存储单元，包括集成选择器件和存储元件
公开(公告)号：US20130069030A1
公开(公告)日：2013-03-21
申请号：US13234875
申请日：2011-09-16
申请人： David H. Wells , D.V. Nirmal Ramaswamy , Kirk D. Prall
发明人： David H. Wells , D.V. Nirmal Ramaswamy , Kirk D. Prall
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L45/085 , G11C2213/73 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/146
摘要： Resistive memory cells including an integrated select device and storage element and methods of forming the same are described herein. As an example, a resistive memory cell can include a select device structure including a Schottky interface, and a storage element integrated with the select device structure such that an electrode corresponding to the Schottky interface serves as a first electrode of the storage element. The storage element can include a storage material formed between the first electrode and a second electrode.
摘要翻译：包括集成选择装置和存储元件的电阻式存储单元及其形成方法在此描述。作为示例，电阻式存储单元可以包括包括肖特基接口的选择器件结构和与选择器件结构集成的存储元件，使得对应于肖特基界面的电极用作存储元件的第一电极。存储元件可以包括形成在第一电极和第二电极之间的存储材料。

9. 发明授权

US08283198B2 Resistive memory and methods of processing resistive memory 有权
标题翻译：电阻记忆和处理电阻记忆的方法
公开(公告)号：US08283198B2
公开(公告)日：2012-10-09
申请号：US12776764
申请日：2010-05-10
申请人： David H. Wells
发明人： David H. Wells
IPC分类号： H01L21/00 , H01L29/08
CPC分类号： H01L45/126 , H01L27/2463 , H01L45/06 , H01L45/144 , H01L45/16
摘要： Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material.
摘要翻译：本文描述了电阻存储器和处理电阻性存储器的方法。处理电阻性存储器的一个或多个方法实施例包括在具有存取装置接触的电极上形成电阻性存储单元材料，以及在电阻上形成电阻式存储单元材料之后，在电阻式存储单元材料上形成加热器电极，使得加热器电极与电阻式存储单元材料自对准。

10. 发明申请

US20100308438A1 NON-CONFORMAL MASKS, SEMICONDUCTOR DEVICE STRUCTURES INCLUDING THE SAME, AND METHODS 有权
标题翻译：非一致性掩模，包括其的半导体器件结构和方法
公开(公告)号：US20100308438A1
公开(公告)日：2010-12-09
申请号：US12477551
申请日：2009-06-03
申请人： David H. Wells
发明人： David H. Wells
IPC分类号： H01L21/027 , H01L23/58
CPC分类号： H01L21/3083 , H01L21/0334 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L21/76224
摘要： A method for fabricating semiconductor device structures includes forming a non-conformal mask over a surface of a substrate. Non-conformal mask material with a planar or substantially planar upper surface is formed on the surface of the substrate. The planarity or substantial planarity of the non-conformal material eliminates or substantially eliminates distortion in a “mask” formed thereover and, thus, eliminates or substantially eliminates distortion in any mask that is subsequently formed using the pattern of the mask. In some embodiments, mask material of the non-conformal mask does not extend into recesses in the upper surface of the substrate; instead it “bridges” the recesses. Semiconductor device structures that include non-conformal masks and semiconductor device structures that have been fabricated with non-conformal masks are also disclosed.
摘要翻译：一种制造半导体器件结构的方法包括在衬底的表面上形成非共形掩模。在基板的表面上形成具有平面或基本平坦的上表面的非保形掩模材料。非保形材料的平面度或实质平面度消除或基本上消除了在其上形成的“掩模”中的失真，并因此消除或基本上消除随后使用掩模图案形成的任何掩模中的畸变。在一些实施例中，非保形掩模的掩模材料不延伸到衬底的上表面中的凹槽中; 而是“桥”了凹槽。还公开了包括使用非保形掩模制造的非共形掩模和半导体器件结构的半导体器件结构。

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