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    • 4. 发明申请
    • IMAGER ARRAY INTERFACES
    • 图像阵列接口
    • US20110279721A1
    • 2011-11-17
    • US13106804
    • 2011-05-12
    • Andrew Kenneth John McMahon
    • Andrew Kenneth John McMahon
    • H04N5/335
    • H04N5/341H04N5/23232H04N5/3415H04N5/345H04N5/3653H04N5/3742H04N5/3745H04N5/378H04N9/045H04N9/09
    • Architectures for imager arrays configured for use in array cameras in accordance with embodiments of the invention are described. One embodiment of the invention includes a plurality of focal planes, where each focal plane comprises a two dimensional arrangement of pixels having at least two pixels in each dimension and each focal plane is contained within a region of the imager array that does not contain pixels from another focal plane, control circuitry configured to control the capture of image information by the pixels within the focal planes, where the control circuitry is configured so that the capture of image information by the pixels in at least two of the focal planes is separately controllable, sampling circuitry configured to convert pixel outputs into digital pixel data, and output interface circuitry configured to transmit pixel data via an output interface.
    • 描述了根据本发明实施例的配置用于阵列相机的成像器阵列的体系结构。 本发明的一个实施例包括多个焦平面,其中每个焦平面包括在每个维度中具有至少两个像素的像素的二维排列,并且每个焦平面包含在不包含像素的像素阵列的区域内 另一个焦平面,控制电路被配置为控制由焦平面内的像素捕捉图像信息,其中控制电路被配置为使得至少两个焦平面中的像素对图像信息的捕获是单独可控的, 配置成将像素输出转换为数字像素数据的采样电路,以及经配置以经由输出接口传输像素数据的输出接口电路。
    • 5. 发明授权
    • Black level calibration method for imager with hysteresis comparison and adaptive step size
    • 具有滞后比较和自适应步长的成像器的黑色电平校准方法
    • US07084911B1
    • 2006-08-01
    • US10290782
    • 2002-11-08
    • Bumha LeeAndrew Kenneth John McMahon
    • Bumha LeeAndrew Kenneth John McMahon
    • H04N9/64H04N9/73H04N5/217H01L27/00
    • H04N5/361
    • The present invention provides a method and apparatus for calibrating a black level in an imager to reduce flicker noise. A first and a second range is set. The first range corresponds to a range that is larger than a noise level at a highest PGA gain. The second range corresponds to a range that is smaller than a level which reduces an ADC dynamic range too much due to a large black level. The ranges may be adjusted to changes in an imager in real time. When the black level is within the second range a determination is made as to whether the black level has been calibrated before. When it has, the DAC output is held constant. Otherwise the DAC code is adjusted such that the black level is moved toward the first range. A small step size is used in adjusting the DAC code in order to reduce flicker. Step sizes may be adjusted according to the black level in relation to the ranges. A small step size is used when the black level is within the second range. A large step size is used when the black level is beyond the second range.
    • 本发明提供了一种用于在成像器中校准黑电平以减少闪烁噪声的方法和装置。 设置第一和第二范围。 第一范围对应于在最高PGA增益下大于噪声电平的范围。 第二范围对应于小于由于大的黑电平而使ADC动态范围过大的电平的范围。 范围可以实时调整成像仪的变化。 当黑色电平处于第二范围内时,确定黑电平是否已被校准。 当它有,DAC输出保持不变。 否则调整DAC代码,使得黑色电平移动到第一范围。 为了减少闪烁,使用小步长调整DAC代码。 可以根据与范围相关的黑色级别调整步长。 当黑色电平在第二范围内时,使用小步长。 当黑色电平超出第二范围时,使用较大的步长。
    • 7. 发明授权
    • Imager array interfaces
    • Imager阵列接口
    • US08928793B2
    • 2015-01-06
    • US13106804
    • 2011-05-12
    • Andrew Kenneth John McMahon
    • Andrew Kenneth John McMahon
    • H04N5/335H04N5/345H04N5/365H04N5/374H04N5/3745H04N5/378H04N9/04
    • H04N5/341H04N5/23232H04N5/3415H04N5/345H04N5/3653H04N5/3742H04N5/3745H04N5/378H04N9/045H04N9/09
    • Architectures for imager arrays configured for use in array cameras in accordance with embodiments of the invention are described. One embodiment of the invention includes a plurality of focal planes, where each focal plane comprises a two dimensional arrangement of pixels having at least two pixels in each dimension and each focal plane is contained within a region of the imager array that does not contain pixels from another focal plane, control circuitry configured to control the capture of image information by the pixels within the focal planes, where the control circuitry is configured so that the capture of image information by the pixels in at least two of the focal planes is separately controllable, sampling circuitry configured to convert pixel outputs into digital pixel data, and output interface circuitry configured to transmit pixel data via an output interface.
    • 描述了根据本发明实施例的配置用于阵列相机的成像器阵列的体系结构。 本发明的一个实施例包括多个焦平面,其中每个焦平面包括在每个维度中具有至少两个像素的像素的二维排列,并且每个焦平面包含在不包含像素的像素阵列的区域内 另一个焦平面,控制电路被配置为控制由焦平面内的像素捕捉图像信息,其中控制电路被配置为使得至少两个焦平面中的像素对图像信息的捕获是单独可控的, 配置成将像素输出转换为数字像素数据的采样电路,以及经配置以经由输出接口传输像素数据的输出接口电路。